{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:27:18Z","timestamp":1750220838225,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":8,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,22]],"date-time":"2019-06-22T00:00:00Z","timestamp":1561161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,22]]},"DOI":"10.1145\/3341069.3341071","type":"proceedings-article","created":{"date-parts":[[2019,8,16]],"date-time":"2019-08-16T19:51:28Z","timestamp":1565985088000},"page":"1-5","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Optimization of Jacobi Iteration on the Intel Xeon Phi"],"prefix":"10.1145","author":[{"given":"Wenxiang","family":"Yang","sequence":"first","affiliation":[{"name":"China Aerodynamics Research and Development Center, Mianyang, China"}]},{"given":"Jiming","family":"Zou","sequence":"additional","affiliation":[{"name":"China Aerodynamics Research and Development Center, Mianyang, China"}]},{"given":"Liang","family":"Deng","sequence":"additional","affiliation":[{"name":"China Aerodynamics Research and Development Center, Mianyang, China, School of Computer Science, National University of Defense Technology, Changsha, China"}]}],"member":"320","published-online":{"date-parts":[[2019,6,22]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Intel\u00ae Xeon Phi\u2122 coprocessor High-performance Programming{M}","author":"Jim Jeffers","year":"2013","unstructured":"Jim Jeffers , James Reinders. Intel\u00ae Xeon Phi\u2122 coprocessor High-performance Programming{M} . US : Morgan Kaufmann Publishers , 2013 . Jim Jeffers, James Reinders. Intel\u00ae Xeon Phi\u2122 coprocessor High-performance Programming{M}. US: Morgan Kaufmann Publishers, 2013."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1137\/070693199"},{"key":"e_1_3_2_1_3_1","volume-title":"Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures{C}\/\/Proceedings of the ACM\/IEEE conference on Supercomputing","author":"Datta K","year":"2008","unstructured":"Datta K , Murphy M , Volkov V , Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures{C}\/\/Proceedings of the ACM\/IEEE conference on Supercomputing . Austin, Texas, USA , 2008 : 4. Datta K, Murphy M, Volkov V, et al. Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures{C}\/\/Proceedings of the ACM\/IEEE conference on Supercomputing. Austin, Texas, USA, 2008: 4."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.2"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPPW.2010.38"},{"key":"e_1_3_2_1_6_1","unstructured":"Intel. Intel Xeon Phi Coprocessor System Software Development Guide Nov.2012.  Intel. Intel Xeon Phi Coprocessor System Software Development Guide Nov.2012."},{"volume-title":"Part 2: Understanding and Using Hardware Events","author":"Optimization","key":"e_1_3_2_1_7_1","unstructured":"Optimization and Performance Tuning for Intel\u00ae Xeon Phi\u2122 Coprocessors , Part 2: Understanding and Using Hardware Events , http:\/\/software.intel.com\/en-us\/articles\/optimization-and-performance-tuning-for-intel-xeon-phi-coprocessors-part-2-understanding 2012-11-12. Optimization and Performance Tuning for Intel\u00ae Xeon Phi\u2122 Coprocessors, Part 2: Understanding and Using Hardware Events, http:\/\/software.intel.com\/en-us\/articles\/optimization-and-performance-tuning-for-intel-xeon-phi-coprocessors-part-2-understanding 2012-11-12."},{"key":"e_1_3_2_1_8_1","unstructured":"An Overview of Programming for Intel\u00ae Xeon\u00ae processors and Intel\u00ae Xeon Phi\u2122 coprocessors(Intel 2012) http:\/\/tinyurl.com\/xeonphisum.  An Overview of Programming for Intel\u00ae Xeon\u00ae processors and Intel\u00ae Xeon Phi\u2122 coprocessors(Intel 2012) http:\/\/tinyurl.com\/xeonphisum."}],"event":{"name":"HPCCT 2019: 2019 The 3rd High Performance Computing and Cluster Technologies Conference","acronym":"HPCCT 2019","location":"Guangzhou China"},"container-title":["Proceedings of the 2019 3rd High Performance Computing and Cluster Technologies Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3341069.3341071","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3341069.3341071","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:13:43Z","timestamp":1750202023000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3341069.3341071"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6,22]]},"references-count":8,"alternative-id":["10.1145\/3341069.3341071","10.1145\/3341069"],"URL":"https:\/\/doi.org\/10.1145\/3341069.3341071","relation":{},"subject":[],"published":{"date-parts":[[2019,6,22]]},"assertion":[{"value":"2019-06-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}