{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:29:19Z","timestamp":1750220959310,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,3,30]],"date-time":"2020-03-30T00:00:00Z","timestamp":1585526400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Ministry of Science and Technology of Taiwan","award":["MOST-108-2918-I-260-005-, MOST-107-2221-E-260-004-MY2, MOST-106-2221-E-260-022-, MOST-105-2221-E-260-024-"],"award-info":[{"award-number":["MOST-108-2918-I-260-005-, MOST-107-2221-E-260-004-MY2, MOST-106-2221-E-260-022-, MOST-105-2221-E-260-024-"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,3,30]]},"DOI":"10.1145\/3341105.3373858","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T17:55:36Z","timestamp":1592243736000},"page":"546-553","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories"],"prefix":"10.1145","author":[{"given":"Chia-Yin","family":"Liu","sequence":"first","affiliation":[{"name":"Tohoku University, Miyagi, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yi-Jung","family":"Chen","sequence":"additional","affiliation":[{"name":"National Chi Nan University, Nantou, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masanori","family":"Hariyama","sequence":"additional","affiliation":[{"name":"Tohoku University, Miyagi, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,3,30]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"ARM processor Cortex-A9. https:\/\/developer.arm.com\/ip-products\/processors\/cortex-a\/cortex-a9.  ARM processor Cortex-A9. https:\/\/developer.arm.com\/ip-products\/processors\/cortex-a\/cortex-a9."},{"key":"e_1_3_2_1_2_1","unstructured":"CACTIC6.5. http:\/\/www.hpl.hp.com\/research\/cacti\/.  CACTIC6.5. http:\/\/www.hpl.hp.com\/research\/cacti\/."},{"key":"e_1_3_2_1_3_1","unstructured":"EEMBC\n  : Embedded microprocessor benchmark consortium. http:\/\/www.eembc.org\/home.php.  EEMBC: Embedded microprocessor benchmark consortium. http:\/\/www.eembc.org\/home.php."},{"key":"e_1_3_2_1_4_1","unstructured":"High Bandwidth Memory (HBM) DRAM. https:\/\/www.jedec.org\/standards-documents\/docs\/jesd235a.  High Bandwidth Memory (HBM) DRAM. https:\/\/www.jedec.org\/standards-documents\/docs\/jesd235a."},{"key":"e_1_3_2_1_5_1","unstructured":"Hornet-1.0. http:\/\/csg.csail.mit.edu\/hornet\/.  Hornet-1.0. http:\/\/csg.csail.mit.edu\/hornet\/."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"crossref","unstructured":"Berkin Akin et al. 2015. Data Reorganization in Memory Using 3D-stacked DRAM. In ISCA.  Berkin Akin et al. 2015. Data Reorganization in Memory Using 3D-stacked DRAM. In ISCA.","DOI":"10.1145\/2749469.2750397"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"crossref","unstructured":"Yi-Jung Chen etal 2012. Distributed Memory Interface Synthesis for Network-on-chips with 3D-stacked DRAMs. In ICCAD.  Yi-Jung Chen et al. 2012. Distributed Memory Interface Synthesis for Network-on-chips with 3D-stacked DRAMs. In ICCAD.","DOI":"10.1145\/2429384.2429479"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"Y. J. Chen etal 2015. A cluster-based reliability- and thermal-aware 3D floor-planning using redundant STSVs. In VLSI-SoC.  Y. J. Chen et al. 2015. A cluster-based reliability- and thermal-aware 3D floor-planning using redundant STSVs. In VLSI-SoC.","DOI":"10.1109\/VLSI-SoC.2015.7314442"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2924715.2924718"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","unstructured":"Yi-Jung Chen Chia-Lin Yang Pin-Sheng Lin and Yi-Chang Lu. 2015. Thermal\/Performance Characterization of CMPs with 3D-stacked DRAMs Under Synergistic Voltage-frequency Control of Cores and DRAMs. In RACS.  Yi-Jung Chen Chia-Lin Yang Pin-Sheng Lin and Yi-Chang Lu. 2015. Thermal\/Performance Characterization of CMPs with 3D-stacked DRAMs Under Synergistic Voltage-frequency Control of Cores and DRAMs. In RACS.","DOI":"10.1145\/2811411.2811515"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TENCONSpring.2013.6584424"},{"volume-title":"Tajana Simunic Rosing, and Yusuf Leblebici","year":"2009","author":"Coskun Ayse K.","key":"e_1_3_2_1_13_1"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/278241.278309"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"Amin Farmahini-Farahani etal 2018. Challenges of High-Capacity DRAM Stacks and Potential Directions. In MCHPC.  Amin Farmahini-Farahani et al. 2018. Challenges of High-Capacity DRAM Stacks and Potential Directions. In MCHPC.","DOI":"10.1145\/3286475.3286484"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"crossref","unstructured":"J. Fu et al. 2015. A novel thermal-aware structure of TSV cluster. In SOCC.  J. Fu et al. 2015. A novel thermal-aware structure of TSV cluster. In SOCC.","DOI":"10.1109\/SOCC.2015.7406993"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"crossref","unstructured":"L. Hou et al. 2015. A thermal-aware distribution method of TSV in 3D IC. In ASICON.  L. Hou et al. 2015. A thermal-aware distribution method of TSV in 3D IC. In ASICON.","DOI":"10.1109\/ASICON.2015.7517067"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2501626.2512457"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","unstructured":"Jiang Lin et al. 2007. Thermal Modeling and Management of DRAM Memory Systems. In ISCA.  Jiang Lin et al. 2007. Thermal Modeling and Management of DRAM Memory Systems. In ISCA.","DOI":"10.1145\/1250662.1250701"},{"key":"e_1_3_2_1_20_1","unstructured":"Chia-Yin Liu etal 2018. Thermal-aware Task and Data Co-Allocation for Multi-Processor System-on-Chips with 3D-stacked Memories. In RACS.  Chia-Yin Liu et al. 2018. Thermal-aware Task and Data Co-Allocation for Multi-Processor System-on-Chips with 3D-stacked Memories. In RACS."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"crossref","unstructured":"Andrea Marongiu Martino Ruggiero and Luca Benini. 2010. Efficient OpenMP Data Mapping for Multicore Platforms with Vertically Stacked Memory. In DATE.  Andrea Marongiu Martino Ruggiero and Luca Benini. 2010. Efficient OpenMP Data Mapping for Multicore Platforms with Vertically Stacked Memory. In DATE.","DOI":"10.1109\/DATE.2010.5457227"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"crossref","unstructured":"Jie Meng et al. 2012. Optimizing Energy Efficiency of 3-D Multicore Systems with Stacked DRAM Under Power and Thermal Constraints. In DAC.  Jie Meng et al. 2012. Optimizing Energy Efficiency of 3-D Multicore Systems with Stacked DRAM Under Power and Thermal Constraints. In DAC.","DOI":"10.1145\/2228360.2228477"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"crossref","unstructured":"Sudeep Pasricha. 2009. Exploring Serial Vertical Interconnects for 3D ICs. In DAC.  Sudeep Pasricha. 2009. Exploring Serial Vertical Interconnects for 3D ICs. In DAC.","DOI":"10.1145\/1629911.1630061"},{"volume-title":"COSMECA: Application Specific Co-synthesis of Memory and Communication Architectures for MPSoC. In DATE.","year":"2006","author":"Sudeep Pasricha","key":"e_1_3_2_1_24_1"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2011.7477494"},{"key":"e_1_3_2_1_26_1","article-title":"Temperature-aware Microarchitecture: Modeling and Implementation. ACM","author":"Kevin Skadron","year":"2004","journal-title":"Trans. Archit. Code Optim."},{"key":"e_1_3_2_1_27_1","article-title":"Design Space Exploration for 3D Architectures","author":"Yuan Xie","year":"2006","journal-title":"J. Emerg. Technol. Comput. Syst."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"crossref","unstructured":"X. Zhou J. Yang Y. Xu Y. Zhang and J. Zhao. 2010. Thermal-Aware Task Scheduling for 3D Multicore Processors. IEEE TPDS (2010).  X. Zhou J. Yang Y. Xu Y. Zhang and J. Zhao. 2010. Thermal-Aware Task Scheduling for 3D Multicore Processors. IEEE TPDS (2010).","DOI":"10.1109\/TPDS.2009.27"},{"key":"e_1_3_2_1_29_1","unstructured":"C. Zhu et al. 2008. Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management. IEEE TCAD (2008).  C. Zhu et al. 2008. Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management. IEEE TCAD (2008)."}],"event":{"name":"SAC '20: The 35th ACM\/SIGAPP Symposium on Applied Computing","sponsor":["SIGAPP ACM Special Interest Group on Applied Computing"],"location":"Brno Czech Republic","acronym":"SAC '20"},"container-title":["Proceedings of the 35th Annual ACM Symposium on Applied Computing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3341105.3373858","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3341105.3373858","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:54:11Z","timestamp":1750204451000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3341105.3373858"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3,30]]},"references-count":28,"alternative-id":["10.1145\/3341105.3373858","10.1145\/3341105"],"URL":"https:\/\/doi.org\/10.1145\/3341105.3373858","relation":{},"subject":[],"published":{"date-parts":[[2020,3,30]]},"assertion":[{"value":"2020-03-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}