{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:25:34Z","timestamp":1750220734319,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":40,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,3,30]],"date-time":"2020-03-30T00:00:00Z","timestamp":1585526400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"HiPEAC Network of Excellence"},{"name":"Ramon y Cajal postdoctoral fellowship","award":["RYC-2013-14717"],"award-info":[{"award-number":["RYC-2013-14717"]}]},{"name":"Juan de la Cierva-Formaci\u00f3n postdoctoral fellowship","award":["FJCI-2017-34095"],"award-info":[{"award-number":["FJCI-2017-34095"]}]},{"name":"SuPerCom European Research Council (ERC) project under the European Union?s Horizon 2020 research and innovation programme","award":["772773"],"award-info":[{"award-number":["772773"]}]},{"name":"Juan de la-Cierva-Incorporacion postdoctoral fellowship","award":["IJCI-2016-27396"],"award-info":[{"award-number":["IJCI-2016-27396"]}]},{"name":"Spanish Ministry of Economy and Competitiveness (MINECO)","award":["TIN2015- 65316-P"],"award-info":[{"award-number":["TIN2015- 65316-P"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,3,30]]},"DOI":"10.1145\/3341105.3373955","type":"proceedings-article","created":{"date-parts":[[2020,3,29]],"date-time":"2020-03-29T12:13:52Z","timestamp":1585484032000},"page":"580-589","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["On the reliability of hardware event monitors in MPSoCs for critical domains"],"prefix":"10.1145","author":[{"given":"Javier","family":"Barrera","sequence":"first","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leonidas","family":"Kosmidis","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamid","family":"Tabani","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Enrico","family":"Mezzetti","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaume","family":"Abella","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mikel","family":"Fernandez","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guillem","family":"Bernat","sequence":"additional","affiliation":[{"name":"Rapita Systems Ltd., UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francisco J.","family":"Cazorla","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,3,30]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2014. ARM Cortex-A53 MPCore Processor. http:\/\/infocenter.arm.com\/help\/topic\/com.arm.doc.ddi0500d\/DDI0500D_cortex_a53_r0p2_trm.pdf  2014. ARM Cortex-A53 MPCore Processor. http:\/\/infocenter.arm.com\/help\/topic\/com.arm.doc.ddi0500d\/DDI0500D_cortex_a53_r0p2_trm.pdf"},{"key":"e_1_3_2_1_2_1","unstructured":"2018. CUDA Binary Utilities. https:\/\/docs.nvidia.com\/pdf\/CUDA_Binary_Utilities.pdf  2018. CUDA Binary Utilities. https:\/\/docs.nvidia.com\/pdf\/CUDA_Binary_Utilities.pdf"},{"key":"e_1_3_2_1_3_1","unstructured":"2019. ARMv8 Reference Manual v8.5 EAC. https:\/\/static.docs.arm.com\/ddi0487\/ea\/DDI0487E_a_armv8_arm.pdf  2019. ARMv8 Reference Manual v8.5 EAC. https:\/\/static.docs.arm.com\/ddi0487\/ea\/DDI0487E_a_armv8_arm.pdf"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.2873870"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","unstructured":"T. Amert et al. 2017. GPU Scheduling on the NVIDIA TX2: Hidden Details Revealed. In RTSS.  T. Amert et al. 2017. GPU Scheduling on the NVIDIA TX2: Hidden Details Revealed. In RTSS.","DOI":"10.1109\/RTSS.2017.00017"},{"key":"e_1_3_2_1_6_1","unstructured":"ARM. 2015. ARM Expects Vehicle Compute Performance to Increase 100x in Next Decade. https:\/\/www.arm.com\/about\/newsroom\/arm-expects-vehicle-compute-performance-to-increase-100x-in-next-decade.php.  ARM. 2015. ARM Expects Vehicle Compute Performance to Increase 100x in Next Decade. https:\/\/www.arm.com\/about\/newsroom\/arm-expects-vehicle-compute-performance-to-increase-100x-in-next-decade.php."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"K. Berezovskyi et al. 2012. Makespan Computation for GPU Threads Running on a Single Streaming Multiprocessor. In ECRTS.  K. Berezovskyi et al. 2012. Makespan Computation for GPU Threads Running on a Single Streaming Multiprocessor. In ECRTS.","DOI":"10.1109\/ECRTS.2012.16"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"crossref","unstructured":"K. Berezovskyi et al. 2016. Measurement-Based Probabilistic Timing Analysis for Graphics Processor Units. In ARCS.  K. Berezovskyi et al. 2016. Measurement-Based Probabilistic Timing Analysis for Graphics Processor Units. In ARCS.","DOI":"10.1007\/978-3-319-30695-7_17"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"A. Betts and A.F. Donaldson. 2013. Estimating the WCET of GPU-Accelerated Applications Using Hybrid Analysis. In ECRTS.  A. Betts and A.F. Donaldson. 2013. Estimating the WCET of GPU-Accelerated Applications Using Hybrid Analysis. In ECRTS.","DOI":"10.1109\/ECRTS.2013.29"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","unstructured":"N. Capodieci et al. 2018. Deadline-based Scheduling for GPU with Preemption Support. In RTSS.  N. Capodieci et al. 2018. Deadline-based Scheduling for GPU with Preemption Support. In RTSS.","DOI":"10.1109\/RTSS.2018.00021"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","unstructured":"D. Dasari et al. 2011. Response Time Analysis of COTS-Based Multicores Considering the Contention on the Shared Memory Bus. In IEEE TrustCom.  D. Dasari et al. 2011. Response Time Analysis of COTS-Based Multicores Considering the Contention on the Shared Memory Bus. In IEEE TrustCom.","DOI":"10.1109\/TrustCom.2011.146"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"E. D\u00edaz et al. 2018. Modelling multicore contention on the AURIX TC27x. In DAC.  E. D\u00edaz et al. 2018. Modelling multicore contention on the AURIX TC27x. In DAC.","DOI":"10.1109\/DAC.2018.8465780"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.112130235"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2017.2766558"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"J. Jalle et al. 2016. Contention-aware performance monitoring counter support for real-time MPSoCs. In SIES.  J. Jalle et al. 2016. Contention-aware performance monitoring counter support for real-time MPSoCs. In SIES.","DOI":"10.1109\/SIES.2016.7509440"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"crossref","unstructured":"Noriaki Suzuki et al. 2013. Coordinated Bank and Cache Coloring for Temporal Protection of Memory Accesses. In CSE. IEEE Computer Society.  Noriaki Suzuki et al. 2013. Coordinated Bank and Cache Coloring for Temporal Protection of Memory Accesses. In CSE. IEEE Computer Society.","DOI":"10.1109\/CSE.2013.106"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"crossref","unstructured":"Renato Mancuso et al. 2013. Real-time cache management framework for multicore architectures. In RTAS. IEEE Computer Society.  Renato Mancuso et al. 2013. Real-time cache management framework for multicore architectures. In RTAS. IEEE Computer Society.","DOI":"10.1109\/RTAS.2013.6531078"},{"key":"e_1_3_2_1_18_1","volume-title":"Rodinia: A benchmark suite for heterogeneous computing. In IISWC.","author":"S. Che","year":"2009","unstructured":"S. Che et al. 2009 . Rodinia: A benchmark suite for heterogeneous computing. In IISWC. S. Che et al. 2009. Rodinia: A benchmark suite for heterogeneous computing. In IISWC."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","unstructured":"S. Che et al. 2010. A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads. IISWC (2010).  S. Che et al. 2010. A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads. IISWC (2010).","DOI":"10.1109\/IISWC.2010.5650274"},{"key":"e_1_3_2_1_20_1","volume-title":"Certification Authorities Software Team (CAST)","author":"Federal Aviation Administration","year":"2016","unstructured":"Federal Aviation Administration , Certification Authorities Software Team (CAST) . 2016 . CAST-32A Multi-core Processors . Federal Aviation Administration, Certification Authorities Software Team (CAST). 2016. CAST-32A Multi-core Processors."},{"key":"e_1_3_2_1_21_1","unstructured":"G. Fernandez et al. 2018. Consumer Electronics Processors for Critical Real-Time Systems: a (Failed) Practical Experience. In ERTS2.  G. Fernandez et al. 2018. Consumer Electronics Processors for Critical Real-Time Systems: a (Failed) Practical Experience. In ERTS 2 ."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3139258.3139275"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"crossref","unstructured":"F. Guet et al. 2016. Probabilistic analysis of cache memories and cache memories impacts on multi-core embedded systems. In SIES.  F. Guet et al. 2016. Probabilistic analysis of cache memories and cache memories impacts on multi-core embedded systems. In SIES.","DOI":"10.1109\/SIES.2016.7509420"},{"key":"e_1_3_2_1_24_1","volume-title":"PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms","author":"H. Yun","year":"2014","unstructured":"H. Yun et al. 2014 . PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms . In RTAS. IEEE Computer Society , 155--166. H. Yun et al. 2014. PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms. In RTAS. IEEE Computer Society, 155--166."},{"key":"e_1_3_2_1_25_1","unstructured":"International Organization for Standardization. 2009. ISO\/DIS 26262. Road Vehicles - Functional Safety.  International Organization for Standardization. 2009. ISO\/DIS 26262. Road Vehicles - Functional Safety."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"crossref","unstructured":"L. Liu et al. 2012. A software memory partition approach for eliminating bank-level interference in multicore systems. In PACT. ACM 367--376.  L. Liu et al. 2012. A software memory partition approach for eliminating bank-level interference in multicore systems. In PACT. ACM 367--376.","DOI":"10.1145\/2370816.2370869"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","unstructured":"F. Mazzocchetti et al. 2019. Performance Analysis and Optimization of Automotive GPUs. In SBAC-PAD.  F. Mazzocchetti et al. 2019. Performance Analysis and Optimization of Automotive GPUs. In SBAC-PAD.","DOI":"10.1109\/SBAC-PAD.2019.00027"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/41.19064"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"crossref","unstructured":"J. Nowotsch et al. 2014. Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement. In ECRTS.  J. Nowotsch et al. 2014. Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement. In ECRTS.","DOI":"10.1109\/ECRTS.2014.20"},{"key":"e_1_3_2_1_30_1","unstructured":"NVIDIA. 2019. CUDA toolkit documentation. Volta instruction set. https:\/\/docs.nvidia.com\/cuda\/cuda-binary-utilities\/index.html#volta  NVIDIA. 2019. CUDA toolkit documentation. Volta instruction set. https:\/\/docs.nvidia.com\/cuda\/cuda-binary-utilities\/index.html#volta"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"crossref","unstructured":"N. Otterness et al. 2017. An Evaluation of the NVIDIA TX1 for Supporting Real-Time Computer-Vision Workloads. In RTAS.  N. Otterness et al. 2017. An Evaluation of the NVIDIA TX1 for Supporting Real-Time Computer-Vision Workloads. In RTAS.","DOI":"10.1109\/RTAS.2017.3"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"crossref","unstructured":"P. K. Valsan etal 2016. Taming Non-Blocking Caches to Improve Isolation in Multicore Real-Time Systems. In RTAS. 161--172.  P. K. Valsan et al. 2016. Taming Non-Blocking Caches to Improve Isolation in Multicore Real-Time Systems. In RTAS. 161--172.","DOI":"10.1109\/RTAS.2016.7461361"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"crossref","unstructured":"Xing Pan and Frank Mueller. 2018. Controller-aware memory coloring for multicore realtime systems. In SAC. ACM 584--592.  Xing Pan and Frank Mueller. 2018. Controller-aware memory coloring for multicore realtime systems. In SAC. ACM 584--592.","DOI":"10.1145\/3167132.3167196"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"crossref","unstructured":"R. Pellizzoni et al. 2010. Worst case delay analysis for memory interference in multicore systems. In DATE.  R. Pellizzoni et al. 2010. Worst case delay analysis for memory interference in multicore systems. In DATE.","DOI":"10.1109\/DATE.2010.5456952"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"crossref","unstructured":"H. Tabani et al. 2019. Assessing the Adherence of an Industrial Autonomous Driving Framework to ISO 26262 Software Guidelines. In DAC. 9.  H. Tabani et al. 2019. Assessing the Adherence of an Industrial Autonomous Driving Framework to ISO 26262 Software Guidelines. In DAC. 9.","DOI":"10.1145\/3316781.3317779"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"crossref","unstructured":"V. Weaver et al. 2013. Non-determinism and overcount on modern hardware performance counter implementations. In ISPASS. 215--224.  V. Weaver et al. 2013. Non-determinism and overcount on modern hardware performance counter implementations. In ISPASS. 215--224.","DOI":"10.1109\/ISPASS.2013.6557172"},{"key":"e_1_3_2_1_38_1","unstructured":"Xilinx. 2019. Rockwell Collins Uses Zynq UltraScale+ RFSoC Devices in Revolutionizing How Arrays are Produced and Fielded: Powered by Xilinx. https:\/\/www.xilinx.com\/video\/corporate\/rockwell-collins-rfsoc-revolutionizing-how-arrays-are-produced.html  Xilinx. 2019. Rockwell Collins Uses Zynq UltraScale+ RFSoC Devices in Revolutionizing How Arrays are Produced and Fielded: Powered by Xilinx. https:\/\/www.xilinx.com\/video\/corporate\/rockwell-collins-rfsoc-revolutionizing-how-arrays-are-produced.html"},{"key":"e_1_3_2_1_39_1","unstructured":"Ming Yang et al. 2018. Avoiding Pitfalls when Using NVIDIA GPUs for Real-Time Tasks in Autonomous Systems. In ECRTS.  Ming Yang et al. 2018. Avoiding Pitfalls when Using NVIDIA GPUs for Real-Time Tasks in Autonomous Systems. In ECRTS."},{"key":"e_1_3_2_1_40_1","unstructured":"H. Yun et al. 2013. MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In RTAS.  H. Yun et al. 2013. MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In RTAS."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"crossref","unstructured":"D. Zaparanuks et al. 2009. Accuracy of performance counter measurements. In ISPASS. 23--32.  D. Zaparanuks et al. 2009. Accuracy of performance counter measurements. In ISPASS. 23--32.","DOI":"10.1109\/ISPASS.2009.4919635"}],"event":{"name":"SAC '20: The 35th ACM\/SIGAPP Symposium on Applied Computing","sponsor":["SIGAPP ACM Special Interest Group on Applied Computing"],"location":"Brno Czech Republic","acronym":"SAC '20"},"container-title":["Proceedings of the 35th Annual ACM Symposium on Applied Computing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3341105.3373955","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3341105.3373955","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:38:29Z","timestamp":1750199909000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3341105.3373955"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3,30]]},"references-count":40,"alternative-id":["10.1145\/3341105.3373955","10.1145\/3341105"],"URL":"https:\/\/doi.org\/10.1145\/3341105.3373955","relation":{},"subject":[],"published":{"date-parts":[[2020,3,30]]},"assertion":[{"value":"2020-03-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}