{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T10:16:24Z","timestamp":1781777784648,"version":"3.54.5"},"reference-count":115,"publisher":"Association for Computing Machinery (ACM)","issue":"6","license":[{"start":{"date-parts":[[2019,9,27]],"date-time":"2019-09-27T00:00:00Z","timestamp":1569542400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2019,11,30]]},"abstract":"<jats:p>The globalization of the semiconductor supply chain introduces ever-increasing security and privacy risks. Two major concerns are IP theft through reverse engineering and malicious modification of the design. The latter concern in part relies on successful reverse engineering of the design as well. IC camouflaging and logic locking are two of the techniques under research that can thwart reverse engineering by end-users or foundries. However, developing low overhead locking\/camouflaging schemes that can resist the ever-evolving state-of-the-art attacks has been a challenge for several years. This article provides a comprehensive review of the state of the art with respect to locking\/camouflaging techniques. We start by defining a systematic threat model for these techniques and discuss how various real-world scenarios relate to each threat model. We then discuss the evolution of generic algorithmic attacks under each threat model eventually leading to the strongest existing attacks. The article then systematizes defences and along the way discusses attacks that are more specific to certain kinds of locking\/camouflaging. The article then concludes by discussing open problems and future directions.<\/jats:p>","DOI":"10.1145\/3342099","type":"journal-article","created":{"date-parts":[[2019,9,27]],"date-time":"2019-09-27T12:33:44Z","timestamp":1569587624000},"page":"1-36","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":83,"title":["IP Protection and Supply Chain Security through Logic Obfuscation"],"prefix":"10.1145","volume":"24","author":[{"given":"Kaveh","family":"Shamsi","sequence":"first","affiliation":[{"name":"ECE Department, University of Florida, Gainesville, Florida"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Meng","family":"Li","sequence":"additional","affiliation":[{"name":"ECE Department, University of Texas at Austin, Austin, Texas"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kenneth","family":"Plaks","sequence":"additional","affiliation":[{"name":"Defense Advanced Research Projects Agency, Arlington, Virginia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Saverio","family":"Fazzari","sequence":"additional","affiliation":[{"name":"Booz Allen Hamilton, Arlington, Virginia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"David Z.","family":"Pan","sequence":"additional","affiliation":[{"name":"ECE Department, University of Texas at Austin, Austin, Texas"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yier","family":"Jin","sequence":"additional","affiliation":[{"name":"ECE Department, University of Florida, Gainesville, Florida"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,9,27]]},"reference":[{"key":"e_1_2_1_1_1","first-page":"235","article-title":"Metal finfet anti-fuse","volume":"15","author":"Adusumilli Praneet","year":"2018","journal-title":"US Patent App."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310217"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the USENIX Conference on Security. 291--306","author":"Alkabani Yousra","year":"2007"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2017.7968235"},{"key":"e_1_2_1_5_1","volume-title":"Houman Homayoun, and Avesta Sasan.","author":"Azar Kimia Zamiri","year":"2019"},{"key":"e_1_2_1_6_1","volume-title":"Riedel","author":"Backes John","year":"2008"},{"key":"e_1_2_1_7_1","doi-asserted-by":"crossref","DOI":"10.1109\/MDT.2010.24","volume-title":"Preventing IC piracy using reconfigurable logic barriers","author":"Baumgarten Alex","year":"2010"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.24"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-013-0068-0"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1016\/0026-2692(92)90067-B"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240857"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST.2018.8607163"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2028166"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687424"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2015.7315145"},{"key":"e_1_2_1_16_1","unstructured":"Chipworks. 2012. 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