{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T15:48:31Z","timestamp":1782920911504,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":184,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,10,12]],"date-time":"2019-10-12T00:00:00Z","timestamp":1570838400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,10,12]]},"DOI":"10.1145\/3352460.3358280","type":"proceedings-article","created":{"date-parts":[[2019,10,11]],"date-time":"2019-10-11T11:16:45Z","timestamp":1570792605000},"page":"166-181","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":95,"title":["EDEN"],"prefix":"10.1145","author":[{"given":"Skanda","family":"Koppula","sequence":"first","affiliation":[{"name":"ETH Z\u00fcrich"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lois","family":"Orosa","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"A. Giray","family":"Ya\u011fl\u0131k\u00e7\u0131","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Roknoddin","family":"Azizi","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Taha","family":"Shahroodi","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Konstantinos","family":"Kanellopoulos","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,10,12]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"\"Intel Xeon CPU E3-1225 \" https:\/\/ark.intel.com\/content\/www\/us\/en\/ark\/products\/52270\/intel-xeon-processor-e3-1225-6m-cache-3-10-ghz.html."},{"key":"e_1_3_2_1_2_1","unstructured":"\"NVIDIA Titan X GPU \" https:\/\/www.nvidia.com\/en-us\/geforce\/products\/10series\/titan-x-pascal\/."},{"key":"e_1_3_2_1_3_1","unstructured":"\"SoftMC Source Code.\" https:\/\/github.com\/CMU-SAFARI\/SoftMC"},{"key":"e_1_3_2_1_4_1","unstructured":"\"The CIFAR-10 Dataset.\" https:\/\/www.cs.toronto.edu\/~kriz\/cifar.html"},{"key":"e_1_3_2_1_5_1","volume-title":"Refresh Enabled Video Analytics (REVA): Implications on Power and Performance of DRAM Supported Embedded Visual Systems,\" in ICCD","author":"Advani S.","year":"2014","unstructured":"S. Advani, N. Chandramoorthy, K. Swaminathan, K. Irick, Y. C. P. Cho, J. Sampson, and V. Narayanan, \"Refresh Enabled Video Analytics (REVA): Implications on Power and Performance of DRAM Supported Embedded Visual Systems,\" in ICCD, 2014."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001138"},{"key":"e_1_3_2_1_7_1","volume-title":"Fused-Layer CNN Accelerators,\" in MICRO","author":"Alwani M.","year":"2016","unstructured":"M. Alwani, H. Chen, M. Ferdman, and P. Milder, \"Fused-Layer CNN Accelerators,\" in MICRO, 2016."},{"key":"e_1_3_2_1_8_1","volume-title":"YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration,\" TCAD","author":"Andri R.","year":"2017","unstructured":"R. Andri, L. Cavigelli, D. Rossi, and L. Benini, \"YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration,\" TCAD, 2017."},{"key":"e_1_3_2_1_9_1","volume-title":"A Convolutional Neural Network Neutrino Event Classifier,\" JINST","author":"Aurisano A.","year":"2016","unstructured":"A. Aurisano, A. Radovic, D. Rocco, A. Himmel, M. Messier, E. Niner, G. Pawloski, F. Psihas, A. Sousa, and P. Vahle, \"A Convolutional Neural Network Neutrino Event Classifier,\" JINST, 2016."},{"key":"e_1_3_2_1_10_1","volume-title":"Refresh Now and Then,\" TC","author":"Baek S.","year":"2013","unstructured":"S. Baek, S. Cho, and R. Melhem, \"Refresh Now and Then,\" TC, 2013."},{"key":"e_1_3_2_1_11_1","volume-title":"Analyzing CUDA Workloads using a Detailed GPU Simulator,\" in ISPASS","author":"Bakhoda A.","year":"2009","unstructured":"A. Bakhoda, G. L. Yuan, W. W. Fung, H. Wong, and T. M. Aamodt, \"Analyzing CUDA Workloads using a Detailed GPU Simulator,\" in ISPASS, 2009."},{"key":"e_1_3_2_1_12_1","volume-title":"Physics-Informed Machine Learning for DRAM Error Modeling,\" in DFT","author":"Baseman E.","year":"2018","unstructured":"E. Baseman, N. Debardeleben, S. Blanchard, J. Moore, O. Tkachenko, K. Ferreira, T. Siddiqua, and V. Sridharan, \"Physics-Informed Machine Learning for DRAM Error Modeling,\" in DFT, 2018."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173177"},{"key":"e_1_3_2_1_14_1","volume-title":"Origami: A 803-GOp\/s\/W Convolutional Network Accelerator,\" TCSVT","author":"Cavigelli L.","year":"2017","unstructured":"L. Cavigelli and L. Benini, \"Origami: A 803-GOp\/s\/W Convolutional Network Accelerator,\" TCSVT, 2017."},{"key":"e_1_3_2_1_15_1","volume-title":"Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization,\" in DATE","author":"Chandrasekar K.","year":"2014","unstructured":"K. Chandrasekar, S. Goossens, C. Weis, M. Koedam, B. Akesson, N. Wehn, and K. Goossens, \"Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization,\" in DATE, 2014."},{"key":"e_1_3_2_1_16_1","volume-title":"DRAMPower: Open-source DRAM Power & Energy Estimation Tool","author":"Chandrasekar K.","year":"2012","unstructured":"K. Chandrasekar, C. Weis, Y. Li, B. Akesson, N. Wehn, and K. Goossens, \"DRAMPower: Open-source DRAM Power & Energy Estimation Tool,\" 2012."},{"key":"e_1_3_2_1_17_1","volume-title":"Improving DRAM Performance by Parallelizing Refreshes with Accesses,\" in HPCA","author":"Chang K. K.","year":"2014","unstructured":"K. K. Chang, D. Lee, Z. Chishti, A. R. Alameldeen, C. Wilkerson, Y. Kim, and O. Mutlu, \"Improving DRAM Performance by Parallelizing Refreshes with Accesses,\" in HPCA, 2014."},{"key":"e_1_3_2_1_18_1","volume-title":"Carnegie Mellon Univ.","author":"Chang K. K.","year":"2017","unstructured":"K. K. Chang, \"Understanding and Improving the Latency of DRAM-Based Memory Systems,\" Ph.D. dissertation, Carnegie Mellon Univ., 2017."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2896377.2901453"},{"key":"e_1_3_2_1_20_1","volume-title":"Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM,\" in HPCA","author":"Chang K. K.","year":"2016","unstructured":"K. K. Chang, P. J. Nair, D. Lee, S. Ghose, M. K. Qureshi, and O. Mutlu, \"Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM,\" in HPCA, 2016."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/3078505.3078590"},{"key":"e_1_3_2_1_22_1","volume-title":"Small-Footprint Keyword Spotting using Deep Neural Networks.\" in ICASSP","author":"Chen G.","year":"2014","unstructured":"G. Chen, C. Parada, and G. Heigold, \"Small-Footprint Keyword Spotting using Deep Neural Networks.\" in ICASSP, 2014."},{"key":"e_1_3_2_1_23_1","volume-title":"TVM: An Automated End-to-End Optimizing Compiler for Deep Learning,\" in OSDI","author":"Chen T.","year":"2018","unstructured":"T. Chen, T. Moreau, Z. Jiang, L. Zheng, S. Jiao, E. Yan, H. Shen, M. Cowan, L. Wang, Y. Hu, L. Ceze, C. Guestrin, and A. Krishnamurthy, \"TVM: An Automated End-to-End Optimizing Compiler for Deep Learning,\" in OSDI, 2018."},{"key":"e_1_3_2_1_24_1","volume-title":"Training Deep Nets with Sublinear Memory Cost,\" arXiv","author":"Chen T.","year":"2016","unstructured":"T. Chen, B. Xu, C. Zhang, and C. Guestrin, \"Training Deep Nets with Sublinear Memory Cost,\" arXiv, 2016."},{"key":"e_1_3_2_1_25_1","volume-title":"Dian-Nao: A Small-Footprint High-Throughput Accelerator for Ubiquitous Machine-Learning,\" ASPLOS","author":"Chen T.","year":"2014","unstructured":"T. Chen, Z. Du, N. Sun, J. Wang, C. Wu, Y. Chen, and O. Temam, \"Dian-Nao: A Small-Footprint High-Throughput Accelerator for Ubiquitous Machine-Learning,\" ASPLOS, 2014."},{"key":"e_1_3_2_1_26_1","volume-title":"Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks,\" JSSC","author":"Chen Y.-H.","year":"2017","unstructured":"Y.-H. Chen, T. Krishna, J. S. Emer, and V. Sze, \"Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks,\" JSSC, 2017."},{"key":"e_1_3_2_1_27_1","volume-title":"Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices,\" JETCAS","author":"Chen Y.-H.","year":"2019","unstructured":"Y.-H. Chen, T.-J. Yang, J. Emer, and V. Sze, \"Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices,\" JETCAS, 2019."},{"key":"e_1_3_2_1_28_1","volume-title":"cuDNN: Efficient Primitives for Deep Learning,\" arXiv","author":"Chetlur S.","year":"2014","unstructured":"S. Chetlur, C. Woolley, P. Vandermersch, J. Cohen, J. Tran, B. Catanzaro, and E. Shelhamer, \"cuDNN: Efficient Primitives for Deep Learning,\" arXiv, 2014."},{"key":"e_1_3_2_1_29_1","volume-title":"PRIME: A Novel Processing-In-Memory Architecture for Neural Network Computation In ReRAM-Based Main Memory,\" in ISCA","author":"Chi P.","year":"2016","unstructured":"P. Chi, S. Li, C. Xu, T. Zhang, J. Zhao, Y. Liu, Y. Wang, and Y. Xie, \"PRIME: A Novel Processing-In-Memory Architecture for Neural Network Computation In ReRAM-Based Main Memory,\" in ISCA, 2016."},{"key":"e_1_3_2_1_30_1","volume-title":"Analysis and Characterization of Inherent Application Resilience for Approximate Computing,\" in DAC","author":"Chippa V. K.","year":"2013","unstructured":"V. K. Chippa, S. T. Chakradhar, K. Roy, and A. Raghunathan, \"Analysis and Characterization of Inherent Application Resilience for Approximate Computing,\" in DAC, 2013."},{"key":"e_1_3_2_1_31_1","volume-title":"A Low Latency and Area Optimized DRAM,\" in ISCA","author":"Choi J.","year":"2015","unstructured":"J. Choi, W. Shin, J. Jang, J. Suh, Y. Kwon, Y. Moon, and L.-S. Kim, \"Multiple Clone Row DRAM: A Low Latency and Area Optimized DRAM,\" in ISCA, 2015."},{"key":"e_1_3_2_1_32_1","volume-title":"Microarchitecture Optimizations for Exploiting Memory-Level Parallelism,\" in ISCA","author":"Chou Y.","year":"2004","unstructured":"Y. Chou, B. Fahs, and S. Abraham, \"Microarchitecture Optimizations for Exploiting Memory-Level Parallelism,\" in ISCA, 2004."},{"key":"e_1_3_2_1_33_1","first-page":"1","volume":"1","author":"Courbariaux M.","year":"2016","unstructured":"M. Courbariaux, I. Hubara, D. Soudry, R. El-Yaniv, and Y. Bengio, \"Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to+ 1 or-1,\" arXiv, 2016.","journal-title":"\"Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to+"},{"key":"e_1_3_2_1_34_1","volume-title":"Optimal Brain Damage,\" in NIPS","author":"Cun Y. L.","year":"1990","unstructured":"Y. L. Cun, J. S. Denker, and S. A. Solla, \"Optimal Brain Damage,\" in NIPS, 1990."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196136"},{"key":"e_1_3_2_1_36_1","volume-title":"Memory Power Management via Dynamic Voltage\/Frequency Scaling,\" in ICAC","author":"David H.","year":"2011","unstructured":"H. David, C. Fallin, E. Gorbatov, U. R. Hanebutte, and O. Mutlu, \"Memory Power Management via Dynamic Voltage\/Frequency Scaling,\" in ICAC, 2011."},{"key":"e_1_3_2_1_37_1","volume-title":"High-Accuracy Low-Precision Training,\" arXiv","author":"Sa C. De","year":"2018","unstructured":"C. De Sa, M. Leszczynski, J. Zhang, A. Marzoev, C. R. Aberger, K. Olukotun, and C. R\u00e9, \"High-Accuracy Low-Precision Training,\" arXiv, 2018."},{"key":"e_1_3_2_1_38_1","volume-title":"Retraining-Based Timing Error Mitigation for Hardware Neural Networks,\" in DATE","author":"Deng J.","year":"2015","unstructured":"J. Deng, Y. Rang, Z. Du, Y. Wang, H. Li, O. Temam, P. Ienne, D. Novo, X. Li, Y. Chen, and C. Wu, \"Retraining-Based Timing Error Mitigation for Hardware Neural Networks,\" in DATE, 2015."},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950392"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196029"},{"key":"e_1_3_2_1_41_1","volume-title":"Learning a Deep Convolutional Network for Image Super-Resolution,\" in ECCV","author":"Dong C.","year":"2014","unstructured":"C. Dong, C. C. Loy, K. He, and X. Tang, \"Learning a Deep Convolutional Network for Image Super-Resolution,\" in ECCV, 2014."},{"key":"e_1_3_2_1_42_1","volume-title":"On the Power of Over-parametrization in Neural Networks with Quadratic Activation,\" arXiv","author":"Du S. S.","year":"2018","unstructured":"S. S. Du and J. D. Lee, \"On the Power of Over-parametrization in Neural Networks with Quadratic Activation,\" arXiv, 2018."},{"key":"e_1_3_2_1_43_1","volume-title":"Improving Data Cache Performance by Pre-executing Instructions Under a Cache Miss,\" in ICS","author":"Dundas J.","year":"1997","unstructured":"J. Dundas and T. Mudge, \"Improving Data Cache Performance by Pre-executing Instructions Under a Cache Miss,\" in ICS, 1997."},{"key":"e_1_3_2_1_44_1","unstructured":"J. D. Dundas \"Improving Processor Performance by Dynamically Pre-Processing the Instruction Stream \" University of Michigan Tech. Rep. 1999."},{"key":"e_1_3_2_1_45_1","volume-title":"TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory,\" ASPLOS","author":"Gao M.","year":"2017","unstructured":"M. Gao, J. Pu, X. Yang, M. Horowitz, and C. Kozyrakis, \"TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory,\" ASPLOS, 2017."},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/3309697.3331482"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/3219617.3219661"},{"key":"e_1_3_2_1_48_1","volume-title":"The Reversible Residual Network: Backpropagation without Storing Activations,\" in NIPS","author":"Gomez A. N.","year":"2017","unstructured":"A. N. Gomez, M. Ren, R. Urtasun, and R. B. Grosse, \"The Reversible Residual Network: Backpropagation without Storing Activations,\" in NIPS, 2017."},{"key":"e_1_3_2_1_49_1","volume-title":"Towards End-to-End Speech Recognition with Recurrent Neural Networks,\" in ICML","author":"Graves A.","year":"2014","unstructured":"A. Graves and N. Jaitly, \"Towards End-to-End Speech Recognition with Recurrent Neural Networks,\" in ICML, 2014."},{"key":"e_1_3_2_1_50_1","volume-title":"Deep Reinforcement Learning for Robotic Manipulation with Asynchronous Off-Policy Updates,\" in ICRA","author":"Gu S.","year":"2017","unstructured":"S. Gu, E. Holly, T. Lillicrap, and S. Levine, \"Deep Reinforcement Learning for Robotic Manipulation with Asynchronous Off-Policy Updates,\" in ICRA, 2017."},{"key":"e_1_3_2_1_51_1","volume-title":"Temperature Aware Refresh for DRAM Performance Improvement in 3D ICs,\" in ISQED","author":"Guan M.","year":"2015","unstructured":"M. Guan and L. Wang, \"Temperature Aware Refresh for DRAM Performance Improvement in 3D ICs,\" in ISQED, 2015."},{"key":"e_1_3_2_1_52_1","volume-title":"Angel-Eye: A Complete Design Flow for Mapping CNN onto Embedded FPGA,\" TCAD","author":"Guo K.","year":"2017","unstructured":"K. Guo, L. Sui, J. Qiu, J. Yu, J. Wang, S. Yao, S. Han, Y. Wang, and H. Yang, \"Angel-Eye: A Complete Design Flow for Mapping CNN onto Embedded FPGA,\" TCAD, 2017."},{"key":"e_1_3_2_1_53_1","volume-title":"On the Retention Time Distribution of Dynamic Random Access Memory (DRAM),\" TED","author":"Hamamoto T.","year":"1998","unstructured":"T. Hamamoto, S. Sugiura, and S. Sawada, \"On the Retention Time Distribution of Dynamic Random Access Memory (DRAM),\" TED, 1998."},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"e_1_3_2_1_55_1","volume-title":"Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding,\" arXiv","author":"Han S.","year":"2015","unstructured":"S. Han, H. Mao, and W. J. Dally, \"Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding,\" arXiv, 2015."},{"key":"e_1_3_2_1_56_1","volume-title":"ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality,\" in HPCA","author":"Hassan H.","year":"2016","unstructured":"H. Hassan, G. Pekhimenko, N. Vijaykumar, V. Seshadri, D. Lee, O. Ergin, and O. Mutlu, \"ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality,\" in HPCA, 2016."},{"key":"e_1_3_2_1_57_1","volume-title":"Energy Efficiency, and Reliability,\" in ISCA","author":"Hassan H.","year":"2019","unstructured":"H. Hassan, M. Patel, J. S. Kim, A. G. Yaglikci, N. Vijaykumar, N. Mansouri Ghiasi, S. Ghose, and O. Mutlu, \"CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability,\" in ISCA, 2019."},{"key":"e_1_3_2_1_58_1","volume-title":"SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies,\" in HPCA","author":"Hassan H.","year":"2017","unstructured":"H. Hassan, N. Vijaykumar, S. Khan, S. Ghose, K. Chang, G. Pekhimenko, D. Lee, O. Ergin, and O. Mutlu, \"SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies,\" in HPCA, 2017."},{"key":"e_1_3_2_1_59_1","volume-title":"Deep Residual Learning for Image Recognition,\" in CVPR","author":"He K.","year":"2016","unstructured":"K. He, X. Zhang, S. Ren, and J. Sun, \"Deep Residual Learning for Image Recognition,\" in CVPR, 2016."},{"key":"e_1_3_2_1_60_1","volume-title":"AMC: AutoML for Model Compression and Acceleration on Mobile Devices,\" in ECCV","author":"He Y.","year":"2018","unstructured":"Y. He, J. Lin, Z. Liu, H. Wang, L.-J. Li, and S. Han, \"AMC: AutoML for Model Compression and Acceleration on Mobile Devices,\" in ECCV, 2018."},{"key":"e_1_3_2_1_61_1","volume-title":"Learning Non-maximum Suppression,\" in CVPR","author":"Hosang J.","year":"2017","unstructured":"J. Hosang, R. Benenson, and B. Schiele, \"Learning Non-maximum Suppression,\" in CVPR, 2017."},{"key":"e_1_3_2_1_62_1","volume-title":"Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations,\" IMLR","author":"Hubara I.","year":"2017","unstructured":"I. Hubara, M. Courbariaux, D. Soudry, R. El-Yaniv, and Y. Bengio, \"Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations,\" IMLR, 2017."},{"key":"e_1_3_2_1_63_1","volume-title":"DenseNet: Implementing Efficient ConvNet Descriptor Pyramids,\" arXiv","author":"Iandola F.","year":"2014","unstructured":"F. Iandola, M. Moskewicz, S. Karayev, R. Girshick, T. Darrell, and K. Keutzer, \"DenseNet: Implementing Efficient ConvNet Descriptor Pyramids,\" arXiv, 2014."},{"key":"e_1_3_2_1_64_1","volume-title":"SqueezeNet: AlexNet-Level Accuracy with 50x Fewer Parameters and &lt","author":"Iandola F. N.","year":"2016","unstructured":"F. N. Iandola, S. Han, M. W. Moskewicz, K. Ashraf, W. J. Dally, and K. Keutzer, \"SqueezeNet: AlexNet-Level Accuracy with 50x Fewer Parameters and &lt; 0.5 mb Model Size,\" arXiv, 2016."},{"key":"e_1_3_2_1_65_1","volume-title":"RAPIDNN: In-Memory Deep Neural Network Acceleration Framework,\" arXiv","author":"Imani M.","year":"2018","unstructured":"M. Imani, M. Samragh, Y. Kim, S. Gupta, F. Koushanfar, and T. Rosing, \"RAPIDNN: In-Memory Deep Neural Network Acceleration Framework,\" arXiv, 2018."},{"key":"e_1_3_2_1_66_1","volume-title":"Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference,\" in CVPR","author":"Jacob B.","year":"2018","unstructured":"B. Jacob, S. Kligys, B. Chen, M. Zhu, M. Tang, A. Howard, H. Adam, and D. Kalenichenko, \"Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference,\" in CVPR, 2018."},{"key":"e_1_3_2_1_67_1","unstructured":"JEDEC Standard \"DDR4 SDRAM Specification (JESD79-4) \" 2012."},{"key":"e_1_3_2_1_68_1","volume-title":"Predicting Organic Reaction Outcomes with Weisfeiler-Lehman Network,\" in NIPS","author":"Jin W.","year":"2017","unstructured":"W. Jin, C. Coley, R. Barzilay, and T. Jaakkola, \"Predicting Organic Reaction Outcomes with Weisfeiler-Lehman Network,\" in NIPS, 2017."},{"key":"e_1_3_2_1_69_1","volume-title":"Borchers et al., \"In-Datacenter Performance Analysis of a Tensor Processing Unit,\" in ISCA","author":"Jouppi N. P.","year":"2017","unstructured":"N. P. Jouppi, C. Young, N. Patil, D. Patterson, G. Agrawal, R. Bajwa, S. Bates, S. Bhatia, N. Boden, A. Borchers et al., \"In-Datacenter Performance Analysis of a Tensor Processing Unit,\" in ISCA, 2017."},{"key":"e_1_3_2_1_70_1","volume-title":"Stripes: Bit-Serial Deep Neural Network Computing,\" in MICRO","author":"Judd P.","year":"2016","unstructured":"P. Judd, J. Albericio, T. Hetherington, T. M. Aamodt, and A. Moshovos, \"Stripes: Bit-Serial Deep Neural Network Computing,\" in MICRO, 2016."},{"key":"e_1_3_2_1_71_1","volume-title":"Approximate Computing with Partially Unreliable Dynamic Random Access Memory-Approximate DRAM,\" in DAC","author":"Jung M.","year":"2016","unstructured":"M. Jung, D. M. Mathew, C. Weis, and N. Wehn, \"Approximate Computing with Partially Unreliable Dynamic Random Access Memory-Approximate DRAM,\" in DAC, 2016."},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1145\/2818950.2818964"},{"key":"e_1_3_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.5555\/557161"},{"key":"e_1_3_2_1_74_1","volume-title":"PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM,\" in DSN","author":"Khan S.","year":"2016","unstructured":"S. Khan, D. Lee, and O. Mutlu, \"PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM,\" in DSN, 2016."},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1145\/2591971.2592000"},{"key":"e_1_3_2_1_76_1","volume-title":"Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines,\" in ICCD","author":"Kim J. S.","year":"2018","unstructured":"J. S. Kim, M. Patel, H. Hassan, and O. Mutlu, \"Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines,\" in ICCD, 2018."},{"key":"e_1_3_2_1_77_1","volume-title":"The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices,\" in HPCA","author":"Kim J. S.","year":"2018","unstructured":"J. S. Kim, M. Patel, H. Hassan, and O. Mutlu, \"The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices,\" in HPCA, 2018."},{"key":"e_1_3_2_1_78_1","volume-title":"D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput,\" in HPCA","author":"Kim J. S.","year":"2019","unstructured":"J. S. Kim, M. Patel, H. Hassan, L. Orosa, and O. Mutlu, \"D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput,\" in HPCA, 2019."},{"key":"e_1_3_2_1_79_1","volume-title":"A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM,\" in ISCA","author":"Kim Y.","year":"2012","unstructured":"Y. Kim, V. Seshadri, D. Lee, J. Liu, and O. Mutlu, \"A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM,\" in ISCA, 2012."},{"key":"e_1_3_2_1_80_1","volume-title":"MIT","author":"Kim Y.","year":"2013","unstructured":"Y. Kim, \"Energy Efficient and Error Resilient Neuromorphic Computing in VLSI,\" Ph.D. dissertation, MIT, 2013."},{"key":"e_1_3_2_1_81_1","volume-title":"Ramulator: A Fast and Extensible DRAM Simulator.\" CAL","author":"Kim Y.","year":"2016","unstructured":"Y. Kim, W. Yang, and O. Mutlu, \"Ramulator: A Fast and Extensible DRAM Simulator.\" CAL, 2016."},{"key":"e_1_3_2_1_82_1","volume-title":"Training a Universal Convolutional Neural Network for Low-, Mid-, and High-Level Vision Using Diverse Datasets and Limited Memory.\" in CVPR","author":"Kokkinos I.","year":"2017","unstructured":"I. Kokkinos, \"UberNet: Training a Universal Convolutional Neural Network for Low-, Mid-, and High-Level Vision Using Diverse Datasets and Limited Memory.\" in CVPR, 2017."},{"key":"e_1_3_2_1_83_1","volume-title":"Development of Real-time ADAS Object Detector for Deployment on CPU,\" in IntelliSys","author":"Kozlov A.","year":"2019","unstructured":"A. Kozlov and D. Osokin, \"Development of Real-time ADAS Object Detector for Deployment on CPU,\" in IntelliSys, 2019."},{"key":"e_1_3_2_1_84_1","volume-title":"ImageNet Classification with Deep Convolutional Neural Networks,\" in NIPS","author":"Krizhevsky A.","year":"2012","unstructured":"A. Krizhevsky, I. Sutskever, and G. E. Hinton, \"ImageNet Classification with Deep Convolutional Neural Networks,\" in NIPS, 2012."},{"key":"e_1_3_2_1_85_1","volume-title":"MAESTRO: An Open-Source Infrastructure for Modeling Dataflows within Deep Learning Accelerators,\" arXiv","author":"Kwon H.","year":"2018","unstructured":"H. Kwon, M. Pellauer, and T. Krishna, \"MAESTRO: An Open-Source Infrastructure for Modeling Dataflows within Deep Learning Accelerators,\" arXiv, 2018."},{"key":"e_1_3_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173176"},{"key":"e_1_3_2_1_87_1","volume-title":"Deep Learning,\" Nature","author":"LeCun Y.","year":"2015","unstructured":"Y. LeCun, Y. Bengio, and G. Hinton, \"Deep Learning,\" Nature, 2015."},{"key":"e_1_3_2_1_88_1","volume-title":"Handwritten Digit Recognition with a Back-Propagation Network,\" in NIPS","author":"LeCun Y.","year":"1990","unstructured":"Y. LeCun, B. E. Boser, J. S. Denker, D. Henderson, R. E. Howard, W. E. Hubbard, and L. D. Jackel, \"Handwritten Digit Recognition with a Back-Propagation Network,\" in NIPS, 1990."},{"key":"e_1_3_2_1_89_1","volume-title":"Gradient-Based Learning Applied to Document Recognition,\" Proceedings of the IEEE","author":"LeCun Y.","year":"1998","unstructured":"Y. LeCun, L. Bottou, Y. Bengio, and P. Haffner, \"Gradient-Based Learning Applied to Document Recognition,\" Proceedings of the IEEE, 1998."},{"key":"e_1_3_2_1_90_1","volume-title":"Learning Algorithms for Classification: A Comparison on Handwritten Digit Recognition,\" CTP-PBSRI","author":"LeCun Y.","year":"1995","unstructured":"Y. LeCun, L. Jackel, L. Bottou, C. Cortes, J. S. Denker, H. Drucker, I. Guyon, U. A. Muller, E. Sackinger, P. Simard, and V. Vapnik, \"Learning Algorithms for Classification: A Comparison on Handwritten Digit Recognition,\" CTP-PBSRI, 1995."},{"key":"e_1_3_2_1_91_1","volume-title":"Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,\" in HPCA","author":"Lee D.","year":"2013","unstructured":"D. Lee, Y. Kim, V. Seshadri, J. Liu, L. Subramanian, and O. Mutlu, \"Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,\" in HPCA, 2013."},{"key":"e_1_3_2_1_92_1","volume-title":"Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-DataPort DRAM,\" in PACT","author":"Lee D.","year":"2015","unstructured":"D. Lee, L. Subramanian, R. Ausavarungnirun, J. Choi, and O. Mutlu, \"Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-DataPort DRAM,\" in PACT, 2015."},{"key":"e_1_3_2_1_93_1","volume-title":"Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms,\" SIGMETRICS","author":"Lee D.","year":"2017","unstructured":"D. Lee, S. Khan, L. Subramanian, S. Ghose, R. Ausavarungnirun, G. Pekhimenko, V. Seshadri, and O. Mutlu, \"Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms,\" SIGMETRICS, 2017."},{"key":"e_1_3_2_1_94_1","volume-title":"Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case,\" in HPCA","author":"Lee D.","year":"2015","unstructured":"D. Lee, Y. Kim, G. Pekhimenko, S. Khan, V. Seshadri, K. Chang, and O. Mutlu, \"Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case,\" in HPCA, 2015."},{"key":"e_1_3_2_1_95_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485964"},{"key":"e_1_3_2_1_96_1","unstructured":"D. Levinthal \"Performance Analysis Guide for Intel Core i7 Processor and Intel Xeon 5500 processors \" https:\/\/software.intel.com\/sites\/products\/collateral\/hpc\/vtune\/performance_analysis_guide.pdf 2009."},{"key":"e_1_3_2_1_97_1","volume-title":"Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications,\" in SC","author":"Li G.","year":"2017","unstructured":"G. Li, S. K. S. Hari, M. Sullivan, T. Tsai, K. Pattabiraman, J. Emer, and S. W. Keckler, \"Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications,\" in SC, 2017."},{"key":"e_1_3_2_1_98_1","volume-title":"Pruning Filters for Efficient Convnets,\" arXiv","author":"Li H.","year":"2016","unstructured":"H. Li, A. Kadav, I. Durdanovic, H. Samet, and H. P. Graf, \"Pruning Filters for Efficient Convnets,\" arXiv, 2016."},{"key":"e_1_3_2_1_99_1","volume-title":"SmartShuttle: Optimizing Off-Chip Memory Accesses for Deep Learning Accelerators,\" in DATE","author":"Li J.","year":"2018","unstructured":"J. Li, G. Yan, W. Lu, S. Jiang, S. Gong, J. Wu, and X. Li, \"SmartShuttle: Optimizing Off-Chip Memory Accesses for Deep Learning Accelerators,\" in DATE, 2018."},{"key":"e_1_3_2_1_100_1","volume-title":"SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator.\" in MICRO","author":"Li S.","year":"2018","unstructured":"S. Li, A. O. Glova, X. Hu, P. Gu, D. Niu, K. T. Malladi, H. Zheng, B. Brennan, and Y. Xie, \"SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator.\" in MICRO, 2018."},{"key":"e_1_3_2_1_101_1","unstructured":"S. Li D. Niu K. T. Malladi H. Zheng B. Brennan and Y. Xie \"Drisa: A Dram-Based Reconfigurable In-Situ Accelerator \" in MICRO."},{"key":"e_1_3_2_1_102_1","volume-title":"Continuous Control with Deep Reinforcement Learning,\" arXiv","author":"Lillicrap T. P.","year":"2015","unstructured":"T. P. Lillicrap, J. J. Hunt, A. Pritzel, N. Heess, T. Erez, Y. Tassa, D. Silver, and D. Wierstra, \"Continuous Control with Deep Reinforcement Learning,\" arXiv, 2015."},{"key":"e_1_3_2_1_103_1","volume-title":"Fixed Point Quantization of Deep Convolutional Networks,\" in ICML","author":"Lin D.","year":"2016","unstructured":"D. Lin, S. Talathi, and S. Annapureddy, \"Fixed Point Quantization of Deep Convolutional Networks,\" in ICML, 2016."},{"key":"e_1_3_2_1_104_1","volume-title":"Microsoft COCO: Common Objects in Context,\" in ECCV","author":"Lin T.-Y.","year":"2014","unstructured":"T.-Y. Lin, M. Maire, S. Belongie, J. Hays, P. Perona, D. Ramanan, P. Doll\u00e1r, and C. L. Zitnick, \"Microsoft COCO: Common Objects in Context,\" in ECCV, 2014."},{"key":"e_1_3_2_1_105_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485928"},{"key":"e_1_3_2_1_106_1","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337161"},{"key":"e_1_3_2_1_107_1","volume-title":"ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration,\" TVLSI","author":"Long Y.","year":"2018","unstructured":"Y. Long, T. Na, and S. Mukhopadhyay, \"ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration,\" TVLSI, 2018."},{"key":"e_1_3_2_1_108_1","unstructured":"S.-L. Lu Y.-C. Lin and C.-L. Yang \"Improving DRAM Latency with Dynamic Asymmetric Subarray \" in MICRO 2015."},{"key":"e_1_3_2_1_109_1","volume-title":"Flexflow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks,\" in HPCA","author":"Lu W.","year":"2017","unstructured":"W. Lu, G. Yan, J. Li, S. Gong, Y. Han, and X. Li, \"Flexflow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks,\" in HPCA, 2017."},{"key":"e_1_3_2_1_110_1","volume-title":"Unreliable Memory Operation on a Convolutional Neural Network Processor,\" in SiPS","author":"Marques J.","year":"2017","unstructured":"J. Marques, J. Andrade, and G. Falcao, \"Unreliable Memory Operation on a Convolutional Neural Network Processor,\" in SiPS, 2017."},{"key":"e_1_3_2_1_111_1","volume-title":"Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field,\" in DSN","author":"Meza J.","year":"2015","unstructured":"J. Meza, Q. Wu, S. Kumar, and O. Mutlu, \"Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field,\" in DSN, 2015."},{"key":"e_1_3_2_1_112_1","unstructured":"Micron \"TN-40-07: Calculating Memory Power for DDR4 SDRAM.\" https:\/\/www.micron.com\/-\/media\/documents\/products\/technical-note\/dram\/tn4007_ddr4_power_calculation.pdf"},{"key":"e_1_3_2_1_113_1","volume-title":"Challenges and Solution Directions,\" in More than Moore Technologies for Next Generation Computer Design","author":"Mutlu O.","year":"2015","unstructured":"O. Mutlu, \"Main Memory Scaling: Challenges and Solution Directions,\" in More than Moore Technologies for Next Generation Computer Design, 2015."},{"key":"e_1_3_2_1_114_1","volume-title":"Techniques for Efficient Processing in Runahead Execution Engines,\" in ISCA","author":"Mutlu O.","year":"2005","unstructured":"O. Mutlu, H. Kim, and Y. N. Patt, \"Techniques for Efficient Processing in Runahead Execution Engines,\" in ISCA, 2005."},{"key":"e_1_3_2_1_115_1","volume-title":"On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor,\" in CAL","author":"Mutlu O.","year":"2005","unstructured":"O. Mutlu, H. Kim, J. Stark, and Y. N. Patt, \"On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor,\" in CAL, 2005."},{"key":"e_1_3_2_1_116_1","volume-title":"Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors,\" in HPCA","author":"Mutlu O.","year":"2003","unstructured":"O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt, \"Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors,\" in HPCA, 2003."},{"key":"e_1_3_2_1_117_1","volume-title":"NullaNet: Training Deep Neural Networks for Reduced-Memory-Access Inference,\" arXiv","author":"Nazemi M.","year":"2018","unstructured":"M. Nazemi, G. Pasandi, and M. Pedram, \"NullaNet: Training Deep Neural Networks for Reduced-Memory-Access Inference,\" arXiv, 2018."},{"key":"e_1_3_2_1_118_1","volume-title":"A Reliability Study on CNNs for Critical Embedded Systems,\" in ICCD","author":"Neggaz M. A.","year":"2018","unstructured":"M. A. Neggaz, I. Alouani, P. R. Lorenzo, and S. Niar, \"A Reliability Study on CNNs for Critical Embedded Systems,\" in ICCD, 2018."},{"key":"e_1_3_2_1_119_1","doi-asserted-by":"crossref","unstructured":"A. Neubeck and L. Van Gool \"Efficient Non-maximum Suppression \" in ICPR 2006.","DOI":"10.1109\/ICPR.2006.479"},{"key":"e_1_3_2_1_120_1","volume-title":"Towards Understanding the Role of Over-Parametrization in Generalization of Neural Networks,\" arXiv","author":"Neyshabur B.","year":"2018","unstructured":"B. Neyshabur, Z. Li, S. Bhojanapalli, Y. LeCun, and N. Srebro, \"Towards Understanding the Role of Over-Parametrization in Generalization of Neural Networks,\" arXiv, 2018."},{"key":"e_1_3_2_1_121_1","volume-title":"Stretchable DRAM Refresh Controller with No Parity-overhead Error Correction Scheme for Energy-efficient DNNs,\" in DAC","author":"Nguyen D.-T.","year":"2019","unstructured":"D.-T. Nguyen, N.-M. Ho, and I.-J. Chang, \"St-DRC: Stretchable DRAM Refresh Controller with No Parity-overhead Error Correction Scheme for Energy-efficient DNNs,\" in DAC, 2019."},{"key":"e_1_3_2_1_122_1","doi-asserted-by":"crossref","unstructured":"D. T. Nguyen H. Kim H.-J. Lee and I.-J. Chang \"An Approximate Memory Architecture for a Reduction of Refresh Power Consumption in Deep Learning Applications \" in ISCAS 2018.","DOI":"10.1109\/ISCAS.2018.8351021"},{"key":"e_1_3_2_1_123_1","volume-title":"Sensitivity and Generalization in Neural Networks: An Empirical Study,\" arXiv","author":"Novak R.","year":"2018","unstructured":"R. Novak, Y. Bahri, D. A. Abolafia, J. Pennington, and J. Sohl-Dickstein, \"Sensitivity and Generalization in Neural Networks: An Empirical Study,\" arXiv, 2018."},{"key":"e_1_3_2_1_124_1","volume-title":"GPU Implementation of Neural Networks,\" JPRR","author":"Oh K.-S.","year":"2004","unstructured":"K.-S. Oh and K. Jung, \"GPU Implementation of Neural Networks,\" JPRR, 2004."},{"key":"e_1_3_2_1_125_1","volume-title":"Cross-Layer Approximations for Neuromorphic Computing: From Devices to Circuits and Systems,\" in DAC","author":"Panda P.","year":"2016","unstructured":"P. Panda, A. Sengupta, S. S. Sarwar, G. Srinivasan, S. Venkataramani, A. Raghunathan, and K. Roy, \"Cross-Layer Approximations for Neuromorphic Computing: From Devices to Circuits and Systems,\" in DAC, 2016."},{"key":"e_1_3_2_1_126_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080254"},{"key":"e_1_3_2_1_127_1","volume-title":"Automatic Differentiation in PyTorch,\" NIPS-W","author":"Paszke A.","year":"2017","unstructured":"A. Paszke, S. Gross, S. Chintala, G. Chanan, E. Yang, Z. DeVito, Z. Lin, A. Desmaison, L. Antiga, and A. Lerer, \"Automatic Differentiation in PyTorch,\" NIPS-W, 2017."},{"key":"e_1_3_2_1_128_1","volume-title":"Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices,\" in DSN","author":"Patel M.","year":"2019","unstructured":"M. Patel, J. S. Kim, H. Hassan, and O. Mutlu, \"Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices,\" in DSN, 2019."},{"key":"e_1_3_2_1_129_1","volume-title":"The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions,\" ISCA","author":"Patel M.","year":"2017","unstructured":"M. Patel, J. S. Kim, and O. Mutlu, \"The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions,\" ISCA, 2017."},{"key":"e_1_3_2_1_130_1","volume-title":"Memory-Centric Accelerator Design for Convolutional Neural Networks.\" in ICCD","author":"Peemen M.","year":"2013","unstructured":"M. Peemen, A. A. Setio, B. Mesman, and H. Corporaal, \"Memory-Centric Accelerator Design for Convolutional Neural Networks.\" in ICCD, 2013."},{"key":"e_1_3_2_1_131_1","volume-title":"Complete and Partial Fault Tolerance of Feedforward Neural Nets,\" TNN","author":"Phatak D. S.","year":"1995","unstructured":"D. S. Phatak and I. Koren, \"Complete and Partial Fault Tolerance of Feedforward Neural Nets,\" TNN, 1995."},{"key":"e_1_3_2_1_132_1","volume-title":"Robustness of Neural Networks against Storage Media Errors,\" arXiv","author":"Qin M.","year":"2017","unstructured":"M. Qin, C. Sun, and D. Vucinic, \"Robustness of Neural Networks against Storage Media Errors,\" arXiv, 2017."},{"key":"e_1_3_2_1_133_1","volume-title":"AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems,\" in DSN","author":"Qureshi M. K.","year":"2015","unstructured":"M. K. Qureshi, D.-H. Kim, S. Khan, P. J. Nair, and O. Mutlu, \"AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems,\" in DSN, 2015."},{"key":"e_1_3_2_1_134_1","volume-title":"A Framework for Quantifying the Resilience of Deep Neural Networks,\" in DAC","author":"Reagen B.","year":"2018","unstructured":"B. Reagen, U. Gupta, L. Pentecost, P. Whatmough, S. K. Lee, N. Mulholland, D. Brooks, and G.-Y. Wei, \"Ares: A Framework for Quantifying the Resilience of Deep Neural Networks,\" in DAC, 2018."},{"key":"e_1_3_2_1_135_1","volume-title":"Highly-Accurate Deep Neural Network Accelerators,\" in ISCA","author":"Reagen B.","year":"2016","unstructured":"B. Reagen, P. Whatmough, R. Adolf, S. Rama, H. Lee, S. K. Lee, J. M. Hern\u00e1ndez-Lobato, G.-Y. Wei, and D. Brooks, \"Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators,\" in ISCA, 2016."},{"key":"e_1_3_2_1_136_1","volume-title":"Open Source Neural Networks in C,\" https:\/\/pjreddie.com\/darknet\/","author":"Redmon J.","year":"2013","unstructured":"J. Redmon, \"Darknet: Open Source Neural Networks in C,\" https:\/\/pjreddie.com\/darknet\/, 2013."},{"key":"e_1_3_2_1_137_1","volume-title":"Faster, Stronger,\" arXiv","author":"Redmon J.","year":"2017","unstructured":"J. Redmon and A. Farhadi, \"YOLO9000: Better, Faster, Stronger,\" arXiv, 2017."},{"key":"e_1_3_2_1_138_1","volume-title":"Generalized Intersection Over Union: A Metric and a Loss for Bounding Box Regression,\" in CVPR","author":"Rezatofighi H.","year":"2019","unstructured":"H. Rezatofighi, N. Tsoi, J. Gwak, A. Sadeghian, I. Reid, and S. Savarese, \"Generalized Intersection Over Union: A Metric and a Loss for Bounding Box Regression,\" in CVPR, 2019."},{"key":"e_1_3_2_1_139_1","author":"Robbins H.","year":"1951","unstructured":"H. Robbins and S. Monro, \"A Stochastic Approximation Method,\" The Annals of Mathematical Statistics, 1951.","journal-title":"\"A Stochastic Approximation Method,\" The Annals of Mathematical Statistics"},{"key":"e_1_3_2_1_140_1","volume-title":"ImageNet Large Scale Visual Recognition Challenge,\" IJCV","author":"Russakovsky O.","year":"2015","unstructured":"O. Russakovsky, J. Deng, H. Su, J. Krause, S. Satheesh, S. Ma, Z. Huang, A. Karpathy, A. Khosla, M. Bernstein, A. C. Berg, and L. Fei-Fei, \"ImageNet Large Scale Visual Recognition Challenge,\" IJCV, 2015."},{"key":"e_1_3_2_1_141_1","volume-title":"On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation,\" arXiv","author":"Salami B.","year":"2018","unstructured":"B. Salami, O. Unsal, and A. Cristal, \"On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation,\" arXiv, 2018."},{"key":"e_1_3_2_1_142_1","volume-title":"Comprehensive Evaluation of Supply Voltage Underscaling in FPGA On-chip Memories,\" in MICRO","author":"Salami B.","year":"2018","unstructured":"B. Salami, O. S. Unsal, and A. C. Kestelman, \"Comprehensive Evaluation of Supply Voltage Underscaling in FPGA On-chip Memories,\" in MICRO, 2018."},{"key":"e_1_3_2_1_143_1","volume-title":"Multi-Level Error-Resilient Neural Networks,\" in ISIT","author":"Salavati A. H.","year":"2012","unstructured":"A. H. Salavati and A. Karbasi, \"Multi-Level Error-Resilient Neural Networks,\" in ISIT, 2012."},{"key":"e_1_3_2_1_144_1","volume-title":"SCALE-Sim: Systolic CNN Accelerator,\" in arXiv","author":"Samajdar A.","year":"2018","unstructured":"A. Samajdar, Y. Zhu, P. N. Whatmough, M. Mattina, and T. Krishna, \"SCALE-Sim: Systolic CNN Accelerator,\" in arXiv, 2018."},{"key":"e_1_3_2_1_145_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485963"},{"key":"e_1_3_2_1_146_1","volume-title":"The Next Generation of On-Device Computer Vision Networks,\" in CVPR","author":"Sandler M.","year":"2018","unstructured":"M. Sandler, A. Howard, M. Zhu, A. Zhmoginov, and L.-C. Chen, \"MobileNetV2: The Next Generation of On-Device Computer Vision Networks,\" in CVPR, 2018."},{"key":"e_1_3_2_1_147_1","volume-title":"A Large-Scale Field Study,\" in SIGMETRICS","author":"Schroeder B.","year":"2009","unstructured":"B. Schroeder, E. Pinheiro, and W.-D. Weber, \"DRAM Errors in the Wild: A Large-Scale Field Study,\" in SIGMETRICS, 2009."},{"key":"e_1_3_2_1_148_1","volume-title":"A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets,\" arXiv","author":"Schuiki F.","year":"2018","unstructured":"F. Schuiki, M. Schaffner, F. K. G\u00fcrkaynak, and L. Benini, \"A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets,\" arXiv, 2018."},{"key":"e_1_3_2_1_149_1","volume-title":"Generating Focused Molecule Libraries for Drug Discovery with Recurrent Neural Networks,\" ACS central science","author":"Segler M. H.","year":"2017","unstructured":"M. H. Segler, T. Kogej, C. Tyrchan, and M. P. Waller, \"Generating Focused Molecule Libraries for Drug Discovery with Recurrent Neural Networks,\" ACS central science, 2017."},{"key":"e_1_3_2_1_150_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"e_1_3_2_1_151_1","volume-title":"In-DRAM Bulk Bitwise Execution Engine,\" arXiv","author":"Seshadri V.","year":"2019","unstructured":"V. Seshadri and O. Mutlu, \"In-DRAM Bulk Bitwise Execution Engine,\" arXiv, 2019."},{"key":"e_1_3_2_1_152_1","volume-title":"ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic In Crossbars,\" ISCA","author":"Shafiee A.","year":"2016","unstructured":"A. Shafiee, A. Nag, N. Muralimanohar, R. Balasubramonian, J. P. Strachan, M. Hu, R. S. Williams, and V. Srikumar, \"ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic In Crossbars,\" ISCA, 2016."},{"key":"e_1_3_2_1_153_1","volume-title":"Outrageously Large Neural Networks: The Sparsely-Gated Mixture-of-Experts Layer,\" arXiv","author":"Shazeer N.","year":"2017","unstructured":"N. Shazeer, A. Mirhoseini, K. Maziarz, A. Davis, Q. Le, G. Hinton, and J. Dean, \"Outrageously Large Neural Networks: The Sparsely-Gated Mixture-of-Experts Layer,\" arXiv, 2017."},{"key":"e_1_3_2_1_154_1","volume-title":"Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer,\" in FCCM","author":"Shen Y.","year":"2017","unstructured":"Y. Shen, M. Ferdman, and P. Milder, \"Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer,\" in FCCM, 2017."},{"key":"e_1_3_2_1_155_1","volume-title":"Fault Resilient Physical Neural Networks on a Single Chip,\" in CASES","author":"Shi W.","year":"2014","unstructured":"W. Shi, Y. Wen, Z. Liu, X. Zhao, D. Boumber, R. Vilalta, and L. Xu, \"Fault Resilient Physical Neural Networks on a Single Chip,\" in CASES, 2014."},{"key":"e_1_3_2_1_156_1","volume-title":"Very Deep Convolutional Networks for Large-Scale Image Recognition,\" arXiv","author":"Simonyan K.","year":"2014","unstructured":"K. Simonyan and A. Zisserman, \"Very Deep Convolutional Networks for Large-Scale Image Recognition,\" arXiv, 2014."},{"key":"e_1_3_2_1_157_1","volume-title":"Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations,\" in ISCA","author":"Son Y. H.","year":"2013","unstructured":"Y. H. Son, O. Seongil, Y. Ro, J. W. Lee, and J. H. Ahn, \"Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations,\" in ISCA, 2013."},{"key":"e_1_3_2_1_158_1","volume-title":"C-Brain: A Deep Learning Accelerator that Tames the Diversity of CNNs through Adaptive Data-Level Parallelization,\" in DAC","author":"Song L.","year":"2016","unstructured":"L. Song, Y. Wang, Y. Han, X. Zhao, B. Liu, and X. Li, \"C-Brain: A Deep Learning Accelerator that Tames the Diversity of CNNs through Adaptive Data-Level Parallelization,\" in DAC, 2016."},{"key":"e_1_3_2_1_159_1","volume-title":"Increasing Processor Performance by Implementing Deeper Pipelines,\" in ISCA","author":"Sprangle E.","year":"2002","unstructured":"E. Sprangle and D. Carmean, \"Increasing Processor Performance by Implementing Deeper Pipelines,\" in ISCA, 2002."},{"key":"e_1_3_2_1_160_1","volume-title":"Dropout: A Simple Way to Prevent Neural Networks from Overfitting,\" JMLR","author":"Srivastava N.","year":"2014","unstructured":"N. Srivastava, G. Hinton, A. Krizhevsky, I. Sutskever, and R. Salakhutdinov, \"Dropout: A Simple Way to Prevent Neural Networks from Overfitting,\" JMLR, 2014."},{"key":"e_1_3_2_1_161_1","volume-title":"Efficient Processing of Deep Neural Networks: A tutorial and Survey,\" Proceedings of the IEEE","author":"Sze V.","year":"2017","unstructured":"V. Sze, Y.-H. Chen, T.-J. Yang, and J. S. Emer, \"Efficient Processing of Deep Neural Networks: A tutorial and Survey,\" Proceedings of the IEEE, 2017."},{"key":"e_1_3_2_1_162_1","volume-title":"Improving Bank-Level Parallelism for Irregular Applications,\" in MICRO","author":"Tang X.","year":"2016","unstructured":"X. Tang, M. Kandemir, P. Yedlapalli, and J. Kotra, \"Improving Bank-Level Parallelism for Irregular Applications,\" in MICRO, 2016."},{"key":"e_1_3_2_1_163_1","doi-asserted-by":"crossref","unstructured":"O. Temam \"A Defect-Tolerant Accelerator for Emerging High-Performance Applications \" in ISCA 2012.","DOI":"10.1109\/ISCA.2012.6237031"},{"key":"e_1_3_2_1_164_1","volume-title":"RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM,\" in ISCA","author":"Tu F.","year":"2018","unstructured":"F. Tu, W. Wu, S. Yin, L. Liu, and S. Wei, \"RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM,\" in ISCA, 2018."},{"key":"e_1_3_2_1_165_1","volume-title":"QUEST: A 7.49 TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm CMOS,\" in ISSCC","author":"Ueyoshi K.","year":"2018","unstructured":"K. Ueyoshi, K. Ando, K. Hirose, S. Takamaeda-Yamazaki, J. Kadomoto, T. Miyata, M. Hamada, T. Kuroda, and M. Motomura, \"QUEST: A 7.49 TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm CMOS,\" in ISSCC, 2018."},{"key":"e_1_3_2_1_166_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627613"},{"key":"e_1_3_2_1_167_1","doi-asserted-by":"crossref","unstructured":"T. Vogelsang \"Understanding the Energy Consumption of Dynamic Random Access Memories \" in MICRO 2010.","DOI":"10.1109\/MICRO.2010.42"},{"key":"e_1_3_2_1_168_1","volume-title":"Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration,\" in MICRO","author":"Wang Y.","year":"2018","unstructured":"Y. Wang, A. Tavakkol, L. Orosa, S. Ghose, N. M. Ghiasi, M. Patel, J. S. Kim, H. Hassan, M. Sadrosadati, and O. Mutlu, \"Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration,\" in MICRO, 2018."},{"key":"e_1_3_2_1_169_1","volume-title":"14.3 A 28nm SoC with a 1.2GHz 568nJ\/Prediction Sparse Deep-Neural-Network Engine with &gt;0.1 Timing Error Rate Tolerance for IoT Applications,\" in ISSCC","author":"Whatmough P. N.","year":"2017","unstructured":"P. N. Whatmough, S. K. Lee, H. Lee, S. Rama, D. Brooks, and G. Wei, \"14.3 A 28nm SoC with a 1.2GHz 568nJ\/Prediction Sparse Deep-Neural-Network Engine with &gt;0.1 Timing Error Rate Tolerance for IoT Applications,\" in ISSCC, 2017."},{"key":"e_1_3_2_1_170_1","volume-title":"Quantized Convolutional Neural Networks for Mobile Devices,\" in CVPR","author":"Wu J.","year":"2016","unstructured":"J. Wu, C. Leng, Y. Wang, Q. Hu, and J. Cheng, \"Quantized Convolutional Neural Networks for Mobile Devices,\" in CVPR, 2016."},{"key":"e_1_3_2_1_171_1","volume-title":"Aggregated Residual Transformations for Deep Neural Networks,\" in CVPR","author":"Xie S.","year":"2017","unstructured":"S. Xie, R. Girshick, P. Doll\u00e1r, Z. Tu, and K. He, \"Aggregated Residual Transformations for Deep Neural Networks,\" in CVPR, 2017."},{"key":"e_1_3_2_1_172_1","volume-title":"ECC: Platform-Independent Energy-Constrained Deep Neural Network Compression via a Bilinear Regression Model,\" in CVPR","author":"Yang H.","year":"2019","unstructured":"H. Yang, Y. Zhu, and J. Liu, \"ECC: Platform-Independent Energy-Constrained Deep Neural Network Compression via a Bilinear Regression Model,\" in CVPR, 2019."},{"key":"e_1_3_2_1_173_1","volume-title":"Privacy-Preserving Convolutional Neural Networks,\" in ISVLSI","author":"Yang L.","year":"2017","unstructured":"L. Yang and B. Murmann, \"Approximate SRAM for Energy-Efficient, Privacy-Preserving Convolutional Neural Networks,\" in ISVLSI, 2017."},{"key":"e_1_3_2_1_174_1","volume-title":"SRAM Voltage Scaling for Energy-Efficient Convolutional Neural Networks,\" in ISQED","author":"Yang L.","year":"2017","unstructured":"L. Yang and B. Murmann, \"SRAM Voltage Scaling for Energy-Efficient Convolutional Neural Networks,\" in ISQED, 2017."},{"key":"e_1_3_2_1_175_1","volume-title":"Designing Energy-Efficient Convolutional Neural Networks using Energy-Aware Pruning,\" in CVPR","author":"Yang T.-J.","year":"2017","unstructured":"T.-J. Yang, Y.-H. Chen, and V. Sze, \"Designing Energy-Efficient Convolutional Neural Networks using Energy-Aware Pruning,\" in CVPR, 2017."},{"key":"e_1_3_2_1_176_1","volume-title":"NetAdapt: Platform-Aware Neural Network Adaptation for Mobile Applications,\" in ECCV","author":"Yang T.-J.","year":"2018","unstructured":"T.-J. Yang, A. Howard, B. Chen, X. Zhang, A. Go, M. Sandler, V. Sze, and H. Adam, \"NetAdapt: Platform-Aware Neural Network Adaptation for Mobile Applications,\" in ECCV, 2018."},{"key":"e_1_3_2_1_177_1","volume-title":"Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism,\" in ISCA","author":"Yu J.","year":"2017","unstructured":"J. Yu, A. Lukefahr, D. Palframan, G. Dasika, R. Das, and S. Mahlke, \"Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism,\" in ISCA, 2017."},{"key":"e_1_3_2_1_178_1","volume-title":"Thundervolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Learning Accelerators,\" in DAC","author":"Zhang J.","year":"2018","unstructured":"J. Zhang, K. Rangineni, Z. Ghodsi, and S. Garg, \"Thundervolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Learning Accelerators,\" in DAC, 2018."},{"key":"e_1_3_2_1_179_1","volume-title":"Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Accelerator,\" in VTS","author":"Zhang J. J.","year":"2018","unstructured":"J. J. Zhang, T. Gu, K. Basu, and S. Garg, \"Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Accelerator,\" in VTS, 2018."},{"key":"e_1_3_2_1_180_1","volume-title":"ApproxANN: An Approximate Computing Framework for Artificial Neural Network,\" in DATE","author":"Zhang Q.","year":"2015","unstructured":"Q. Zhang, T. Wang, Y. Tian, F. Yuan, and Q. Xu, \"ApproxANN: An Approximate Computing Framework for Artificial Neural Network,\" in DATE, 2015."},{"key":"e_1_3_2_1_181_1","volume-title":"Cambricon-X: An Accelerator for Sparse Neural Networks,\" in MICRO","author":"Zhang S.","year":"2016","unstructured":"S. Zhang, Z. Du, L. Zhang, H. Lan, S. Liu, L. Li, Q. Guo, T. Chen, and Y. Chen, \"Cambricon-X: An Accelerator for Sparse Neural Networks,\" in MICRO, 2016."},{"key":"e_1_3_2_1_182_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665724"},{"key":"e_1_3_2_1_183_1","volume-title":"AWARD: Approximation-aWAre Restore in Further Scaling DRAM,\" in MEMSYS","author":"Zhang X.","year":"2016","unstructured":"X. Zhang, Y. Zhang, B. Childers, and J. Yang, \"AWARD: Approximation-aWAre Restore in Further Scaling DRAM,\" in MEMSYS, 2016."},{"key":"e_1_3_2_1_184_1","volume-title":"Trained Ternary Quantization,\" arXiv","author":"Zhu C.","year":"2016","unstructured":"C. Zhu, S. Han, H. Mao, and W. J. Dally, \"Trained Ternary Quantization,\" arXiv, 2016."}],"event":{"name":"MICRO '52: The 52nd Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Columbus OH USA","acronym":"MICRO '52","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE CS"]},"container-title":["Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3352460.3358280","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3352460.3358280","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,29]],"date-time":"2025-07-29T22:27:14Z","timestamp":1753828034000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3352460.3358280"}},"subtitle":["Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM"],"short-title":[],"issued":{"date-parts":[[2019,10,12]]},"references-count":184,"alternative-id":["10.1145\/3352460.3358280","10.1145\/3352460"],"URL":"https:\/\/doi.org\/10.1145\/3352460.3358280","relation":{},"subject":[],"published":{"date-parts":[[2019,10,12]]},"assertion":[{"value":"2019-10-12","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}