{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,13]],"date-time":"2026-05-13T02:06:52Z","timestamp":1778638012284,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":40,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,10,12]],"date-time":"2019-10-12T00:00:00Z","timestamp":1570838400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1453378, 1618275"],"award-info":[{"award-number":["1453378, 1618275"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,10,12]]},"DOI":"10.1145\/3352460.3358283","type":"proceedings-article","created":{"date-parts":[[2019,10,11]],"date-time":"2019-10-11T11:16:45Z","timestamp":1570792605000},"page":"139-150","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":38,"title":["Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating"],"prefix":"10.1145","author":[{"given":"Weizhe","family":"Hua","sequence":"first","affiliation":[{"name":"Cornell University, Ithaca, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan","family":"Zhou","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christopher","family":"De Sa","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiru","family":"Zhang","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G. Edward","family":"Suh","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,10,12]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"An Analysis of Deep Neural Network Models for Practical Applications. arXiv preprint arXiv:1605.07678","author":"Canziani A.","year":"2016","unstructured":"A. Canziani, A. Paszke, and E. Culurciello. An Analysis of Deep Neural Network Models for Practical Applications. arXiv preprint arXiv:1605.07678, 2016."},{"key":"e_1_3_2_1_2_1","volume-title":"Int'l Conf. on Multimedia (MM)","author":"Lu Z.","year":"2017","unstructured":"Z. Lu, S. Rallapalli, K. S. Chan, and T. F. La Porta. Modeling the Resource Requirements of Convolutional Neural Networks on Mobile Devices. In Int'l Conf. on Multimedia (MM), Oct 2017."},{"key":"e_1_3_2_1_3_1","volume-title":"Int'l Conf. on Learning Representations (ICLR)","author":"Han S.","year":"2016","unstructured":"S. Han, H. Mao, and W. J. Dally. Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding. In Int'l Conf. on Learning Representations (ICLR), May 2016."},{"key":"e_1_3_2_1_4_1","volume-title":"Int'l Conf. on Learning Representations (ICLR)","author":"Li H.","year":"2017","unstructured":"H. Li, A. Kadav, I. Durdanovic, H. Samet, and H. P. Graf. Pruning Filters for Efficient ConvNets. In Int'l Conf. on Learning Representations (ICLR), May 2017."},{"key":"e_1_3_2_1_5_1","volume-title":"Int'l Conf. on Computer Vision (ICCV)","author":"Liu Z.","year":"2017","unstructured":"Z. Liu, J. Li, Z. Shen, G. Huang, S. Yan, and C. Zhang. Learning Efficient Convolutional Networks through Network Slimming. In Int'l Conf. on Computer Vision (ICCV), Oct 2017."},{"key":"e_1_3_2_1_6_1","volume-title":"Int'l Conf. on Computer Vision (ICCV)","author":"He Y.","year":"2017","unstructured":"Y. He, X. Zhang, and J. Sun. Channel Pruning for Accelerating Very Deep Neural Networks. In Int'l Conf. on Computer Vision (ICCV), Oct 2017."},{"key":"e_1_3_2_1_7_1","volume-title":"Int'l Symp. on Computer Architecture (ISCA)","author":"Albericio J.","year":"2016","unstructured":"J. Albericio, P. Judd, T. Hetherington, T. Aamodt, N. E. Jerger, and A. Moshovos. Cnvlutin: Ineffectual-neuron-free Deep Neural Network Computing. In Int'l Symp. on Computer Architecture (ISCA), Jun 2016."},{"key":"e_1_3_2_1_8_1","volume-title":"Highly-Accurate Deep Neural Network Accelerators. In Int'l Symp. on Computer Architecture (ISCA)","author":"Reagen B.","year":"2016","unstructured":"B. Reagen, P. Whatmough, R. Adolf, S. Rama, H. Lee, S. K. Lee, J. M. Hern\u00c3\u0105ndez-Lobato, G. Y. Wei, and D. Brooks. Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators. In Int'l Symp. on Computer Architecture (ISCA), Jun 2016."},{"key":"e_1_3_2_1_9_1","volume-title":"Int'l Symp. on Computer Architecture (ISCA)","author":"Akhlaghi V.","year":"2018","unstructured":"V. Akhlaghi, A. Yazdanbakhsh, K. Samadi, R. K. Gupta, and H. Esmaeilzadeh. SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks. In Int'l Symp. on Computer Architecture (ISCA), Jun 2018."},{"key":"e_1_3_2_1_10_1","volume-title":"SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <1MB model size. arXiv preprint arXiv:1602.07360","author":"Iandola F. N.","year":"2016","unstructured":"F. N. Iandola, M. W. Moskewicz, K. Ashraf, S. Han, W. J. Dally, and K. Keutzer. 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Zhang. MXNet: A Flexible and Efficient Machine Learning Library for Heterogeneous Distributed Systems. arXiv preprint arXiv: 1512.01274, 2015."},{"key":"e_1_3_2_1_14_1","volume-title":"Channel Gating Neural Networks. arXiv preprint arXiv","author":"Hua W.","year":"1805","unstructured":"W. Hua, C. De Sa, Z. Zhang, and G. E. Suh. Channel Gating Neural Networks. arXiv preprint arXiv: 1805.12549, 2018."},{"key":"e_1_3_2_1_15_1","volume-title":"Int'l Symp. on Field-Programmable Gate Arrays (FPGA)","author":"Zhang C.","year":"2015","unstructured":"C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao, and J. Cong. Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. In Int'l Symp. on Field-Programmable Gate Arrays (FPGA), Feb 2015."},{"key":"e_1_3_2_1_16_1","volume-title":"Int'l Symp. on Field-Programmable Gate Arrays (FPGA)","author":"J. Qiu","year":"2016","unstructured":"J. Qiu et al. Going deeper with embedded fpga platform for convolutional neural network. In Int'l Symp. on Field-Programmable Gate Arrays (FPGA), Feb 2016."},{"key":"e_1_3_2_1_17_1","volume-title":"Int'l Symp. on Field-Programmable Gate Arrays (FPGA)","author":"Zhang J.","year":"2017","unstructured":"J. Zhang and J. Li. Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network. In Int'l Symp. on Field-Programmable Gate Arrays (FPGA), Feb 2017."},{"key":"e_1_3_2_1_18_1","volume-title":"Int'l Symp. on Field-Programmable Gate Arrays (FPGA)","author":"Zhao R.","year":"2017","unstructured":"R. Zhao, W. Song, W. Zhang, T. Xing, J. Lin, M. Srivastava, R. Gupta, and Z. Zhang. Accelerating binarized convolutional neural networks with software-programmable fpgas. In Int'l Symp. on Field-Programmable Gate Arrays (FPGA), Feb 2017."},{"key":"e_1_3_2_1_19_1","volume-title":"Int'l Symp. on Computer Architecture (ISCA)","author":"Han S.","year":"2016","unstructured":"S. Han, X. Liu, H. Mao, J. Pu, A. Pedram, M. A. Horowitz, and W. J. Dally. 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Donahue, S. Karayev, J. Long, R. Girshick, S. Guadarrama, and T. Darrell. Caffe: Convolutional Architecture for Fast Feature Embedding. arXiv preprint arXiv:1408.5093, 2014."},{"key":"e_1_3_2_1_28_1","volume-title":"PACT: Parameterized Clipping Activation for Quantized Neural Networks. arXiv preprint arXiv:1805.06085","author":"Choi J.","year":"2018","unstructured":"J. Choi, Z. Wang, S. Venkataramani, P. I. Chuang, V. Srinivasan, and K. Gopalakrishnan. PACT: Parameterized Clipping Activation for Quantized Neural Networks. arXiv preprint arXiv:1805.06085, 2018."},{"key":"e_1_3_2_1_29_1","author":"Rosenfeld P.","year":"2011","unstructured":"P. Rosenfeld, E. Cooper-Balis, and B. Jacob. DRAMSim2: A Cycle Accurate Memory System Simulator. IEEE Computer Architecture Letters, 2011.","journal-title":"DRAMSim2: A Cycle Accurate Memory System Simulator. IEEE Computer Architecture Letters"},{"key":"e_1_3_2_1_30_1","unstructured":"Hybrid Memory Cube Consortium. Hybrid Memory Cube Specification 2.1. http:\/\/hybridmemorycube.org\/files\/SiteDownloads\/HMC-30G-VSR_HMCC_Specification_Rev2.1_20151105.pdf 2014."},{"key":"e_1_3_2_1_31_1","author":"Azarkhish E.","year":"2018","unstructured":"E. Azarkhish, D. Rossi, I. Loi, and L. Benini. Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes. IEEE Transactions on Parallel and Distributed Systems, 2018.","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"e_1_3_2_1_32_1","author":"Jeon D.","year":"2017","unstructured":"D. Jeon and K. Chung. CasHMC: A Cycle-Accurate Simulator for Hybrid Memory Cube. IEEE Computer Architecture Letters, 2017.","journal-title":"CasHMC: A Cycle-Accurate Simulator for Hybrid Memory Cube. IEEE Computer Architecture Letters"},{"key":"e_1_3_2_1_33_1","volume-title":"Spatially Adaptive Computation Time for Residual Networks. In Conf. on Computer Vision and Pattern Recognition (CVPR)","author":"Figurnov M.","year":"2017","unstructured":"M. Figurnov, M. D. Collins, Y. Zhu, L. Zhang, J. Huang, D. P. Vetrov, and R. Salakhutdinov. Spatially Adaptive Computation Time for Residual Networks. In Conf. on Computer Vision and Pattern Recognition (CVPR), Jul 2017."},{"key":"e_1_3_2_1_34_1","volume-title":"Deep Residual Learning for Image Recognition. In Conf. on Computer Vision and Pattern Recognition (CVPR), Jun\/Jul","author":"He K.","year":"2016","unstructured":"K. He, X. Zhang, S. Ren, and J. Sun. Deep Residual Learning for Image Recognition. In Conf. on Computer Vision and Pattern Recognition (CVPR), Jun\/Jul 2016."},{"key":"e_1_3_2_1_35_1","volume-title":"Runtime Neural Pruning. In Conf. on Neural Information Processing Systems (NeurIPS)","author":"Lin J.","year":"2017","unstructured":"J. Lin, Y. Rao, J. Lu, and J. Zhou. Runtime Neural Pruning. In Conf. on Neural Information Processing Systems (NeurIPS), Dec 2017."},{"key":"e_1_3_2_1_36_1","volume-title":"Int'l Symp. on Circuits and Systems (ISCAS)","author":"Lin Y.","year":"2017","unstructured":"Y. Lin, C. Sakr, Y. Kim, and N. Shanbhag. PredictiveNet: An Energy-Efficient Convolutional Neural Network via Zero Prediction. In Int'l Symp. on Circuits and Systems (ISCAS), May 2017."},{"key":"e_1_3_2_1_37_1","volume-title":"Int'l Symp. on Computer Architecture (ISCA)","author":"Song M.","year":"2018","unstructured":"M. Song, J. Zhao, Y. Hu, J. Zhang, and T. Li. Prediction Based Execution on Deep Neural Networks. In Int'l Symp. on Computer Architecture (ISCA), Jun 2018."},{"key":"e_1_3_2_1_38_1","volume-title":"Int'l Symp. on Computer Architecture (ISCA)","author":"Sharma H.","year":"2018","unstructured":"H. Sharma, J. Park, N. Suda, L. Lai, B. Chau, V. Chandra, and H. Esmaeilzadeh. Bit Fusion: Bit-level Dynamically Composable Architecture for Accelerating Deep Neural Networks. In Int'l Symp. on Computer Architecture (ISCA), Jun 2018."},{"key":"e_1_3_2_1_39_1","volume-title":"Int'l Symp. on Microarchitecture (MICRO)","author":"C. Ding","year":"2017","unstructured":"C. Ding et al. CirCNN: Accelerating and Compressing Deep Neural Networks Using Block-circulant Weight Matrices. In Int'l Symp. on Microarchitecture (MICRO), Oct 2017."},{"key":"e_1_3_2_1_40_1","volume-title":"Int'l Symp. on Microarchitecture (MICRO)","author":"Deng C.","year":"2018","unstructured":"C. Deng, S. Liao, Y. Xie, K. K. Parhi, X. Qian, and B. Yuan. PermDNN: Efficient Compressed DNN Architecture with Permuted Diagonal Matrices. In Int'l Symp. on Microarchitecture (MICRO), Oct 2018."}],"event":{"name":"MICRO '52: The 52nd Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Columbus OH USA","acronym":"MICRO '52","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE CS"]},"container-title":["Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3352460.3358283","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3352460.3358283","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3352460.3358283","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,29]],"date-time":"2025-07-29T22:26:35Z","timestamp":1753827995000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3352460.3358283"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10,12]]},"references-count":40,"alternative-id":["10.1145\/3352460.3358283","10.1145\/3352460"],"URL":"https:\/\/doi.org\/10.1145\/3352460.3358283","relation":{},"subject":[],"published":{"date-parts":[[2019,10,12]]},"assertion":[{"value":"2019-10-12","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}