{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T18:19:00Z","timestamp":1771697940482,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":86,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,10,12]],"date-time":"2019-10-12T00:00:00Z","timestamp":1570838400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS 17-63658, CCF 17-25734, CCF 16-29431"],"award-info":[{"award-number":["CNS 17-63658, CCF 17-25734, CCF 16-29431"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,10,12]]},"DOI":"10.1145\/3352460.3358285","type":"proceedings-article","created":{"date-parts":[[2019,10,11]],"date-time":"2019-10-11T11:16:45Z","timestamp":1570792605000},"page":"384-398","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Tangram"],"prefix":"10.1145","author":[{"given":"Raghavendra Pradyumna","family":"Pothukuchi","sequence":"first","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, Illinois, USA"}]},{"given":"Joseph L.","family":"Greathouse","sequence":"additional","affiliation":[{"name":"Advanced Micro Devices, Inc., Austin, Texas, USA"}]},{"given":"Karthik","family":"Rao","sequence":"additional","affiliation":[{"name":"Advanced Micro Devices, Inc., Austin, Texas, USA"}]},{"given":"Christopher","family":"Erb","sequence":"additional","affiliation":[{"name":"Advanced Micro Devices, Inc., Austin, Texas, USA"}]},{"given":"Leonardo","family":"Piga","sequence":"additional","affiliation":[{"name":"Advanced Micro Devices, Inc., Austin, Texas, USA"}]},{"given":"Petros G.","family":"Voulgaris","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, Illinois, USA"}]},{"given":"Josep","family":"Torrellas","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, Illinois, USA"}]}],"member":"320","published-online":{"date-parts":[[2019,10,12]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2976739"},{"key":"e_1_3_2_1_2_1","unstructured":"Advanced Micro Devices Inc. 2011. AMD FX Processors Unleashed | a Guide to Performance Tuning with AMD OverDrive and the new AMD FX Processors. https:\/\/www.amd.com\/Documents\/AMD_FX_Performance_Tuning_Guide.pdf. Advanced Micro Devices Inc."},{"key":"e_1_3_2_1_3_1","unstructured":"Advanced Micro Devices Inc. 2015. BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 10h-1FFh Processors. http:\/\/developer.amd.com\/resources\/developer-guides-manuals\/. Advanced Micro Devices Inc."},{"key":"e_1_3_2_1_4_1","unstructured":"Advanced Micro Devices Inc. 2018. BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 70h-7Fh Processors. http:\/\/developer.amd.com\/resources\/developer-guides-manuals\/. Advanced Micro Devices Inc."},{"key":"e_1_3_2_1_5_1","unstructured":"Advanced Micro Devices Inc. 2018. Understanding Power Management and Processor Performance Determinism. https:\/\/www.amd.com\/system\/files\/documents\/understanding-power-management.pdf. Whitepaper."},{"key":"e_1_3_2_1_6_1","unstructured":"Advanced Micro Devices Inc. 2019. AMD Radeon RX 580 Graphics. https:\/\/www.amd.com\/en\/products\/graphics\/radeon-rx-580. Accessed: 2019."},{"key":"e_1_3_2_1_7_1","unstructured":"Advanced Micro Devices Inc. 2019. AMD Ryzen. http:\/\/www.amd.com\/en\/ryzen. Accessed: 2019."},{"key":"e_1_3_2_1_8_1","unstructured":"Advanced Micro Devices Inc. 2019. AMD Ryzen Mobile Processors with Radeon Vega Graphics. https:\/\/www.amd.com\/en\/products\/ryzen-processors-laptop. Accessed: 2019."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACC.2012.6314995"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080231"},{"key":"e_1_3_2_1_11_1","volume-title":"Airavat: Improving Energy Efficiency of Heterogeneous Applications. In Conference on Design, Automation and Test in Europe.","author":"Baruah Trinayan","year":"2018","unstructured":"Trinayan Baruah, Yifan Sun, Shi Dong, David Kaeli, and Norm Rubin. 2018. Airavat: Improving Energy Efficiency of Heterogeneous Applications. In Conference on Design, Automation and Test in Europe."},{"key":"e_1_3_2_1_12_1","volume-title":"The Need for Speed and Stability in Data Center Power Capping. In International Green Computing Conference.","author":"Bhattacharya Arka A.","year":"2012","unstructured":"Arka A. Bhattacharya, David Culler, Aman Kansal, Sriram Govindan, and Sriram Sankar. 2012. The Need for Speed and Stability in Data Center Power Capping. In International Green Computing Conference."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_14_1","volume-title":"Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach. In International Symposium on Microarchitecture.","author":"Bitirgen Ramazan","unstructured":"Ramazan Bitirgen, Engin Ipek, and Jose F. Martinez. 2008. Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach. In International Symposium on Microarchitecture."},{"key":"e_1_3_2_1_15_1","volume-title":"EPYC: A Study in Energy Efficient CPU Design. https:\/\/www.amd.com\/system\/files\/documents\/The-Energy-Efficient-AMD-EPYC-Design.pdf.","author":"Brookwood Nathan","year":"2018","unstructured":"Nathan Brookwood. 2018. EPYC: A Study in Energy Efficient CPU Design. https:\/\/www.amd.com\/system\/files\/documents\/The-Energy-Efficient-AMD-EPYC-Design.pdf."},{"key":"e_1_3_2_1_16_1","volume-title":"Silva","author":"Broyles Martha","year":"2015","unstructured":"Martha Broyles, Christopher J. Cain, Todd Rosedahl, and Guillermo J. Silva. 2015. IBM EnergyScale for POWER8 Processor-Based Systems. Technical Report. IBM."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2873584"},{"key":"e_1_3_2_1_18_1","volume-title":"Power Regulation in High Performance Multicore Processors. In IEEE Conference on Decision and Control.","author":"Chen Xinwei","year":"2017","unstructured":"Xinwei Chen, Yorai Wardi, and Sudhakar Yalamanchili. 2017. Power Regulation in High Performance Multicore Processors. In IEEE Conference on Decision and Control."},{"key":"e_1_3_2_1_19_1","volume-title":"Hot Chips: A Symposium on High Performance Chips. Intel Corporation.","author":"Chennupaty Srinivas","year":"2018","unstructured":"Srinivas Chennupaty. 2018. Thin & Light & High Performance Graphics. https:\/\/www.hotchips.org\/hc30\/1conf\/1.04_Intel_Thin_Light_Gaming_HotChips_SC_Final.pdf. In Hot Chips: A Symposium on High Performance Chips. Intel Corporation."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155641"},{"key":"e_1_3_2_1_21_1","unstructured":"Intel Corporation. 2009. Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1. https:\/\/www.intel.ie\/content\/www\/ie\/en\/power-management\/voltage-regulator-module-enterprise-voltage-regulator-down-11-1-guidelines.html. Accessed: 2019."},{"key":"e_1_3_2_1_22_1","unstructured":"Intel Corporation. 2015. Intel Dynamic Platform and Thermal Framework (DPTF) for Chromium OS. https:\/\/01.org\/intel%C2%AE-dynamic-platform-and-thermal-framework-dptf-chromium-os\/documentation\/implementation-design-and-source-code-organization. Accessed: 2019."},{"key":"e_1_3_2_1_23_1","volume-title":"CoScale: Coordinating CPU and Memory System DVFS in Server Systems. In International Symposium on Microarchitecture.","author":"Deng Qingyuan","year":"2012","unstructured":"Qingyuan Deng, David Meisner, Abhishek Bhattacharjee, Thomas F. Wenisch, and Ricardo Bianchini. 2012. CoScale: Coordinating CPU and Memory System DVFS in Server Systems. In International Symposium on Microarchitecture."},{"key":"e_1_3_2_1_24_1","unstructured":"NASA Advanced Supercomputing Division. 2003. NAS Parallel Benchmarks. https:\/\/www.nas.nasa.gov\/publications\/npb.html."},{"key":"e_1_3_2_1_25_1","volume-title":"Performance and Robustness Analysis for Structured Uncertainty. In IEEE Conference on Decision and Control.","author":"Doyle John C.","year":"1982","unstructured":"John C. Doyle, Joseph E. Wall, and Gunter Stein. 1982. Performance and Robustness Analysis for Structured Uncertainty. In IEEE Conference on Decision and Control."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541228.2541238"},{"key":"e_1_3_2_1_27_1","volume-title":"The Computational Sprinting Game. In International Conference on Architectural Support for Programming Languages and Operating Systems.","author":"Fan Songchun","unstructured":"Songchun Fan, Seyed Majid Zahedi, and Benjamin C. Lee. 2016. The Computational Sprinting Game. In International Conference on Architectural Support for Programming Languages and Operating Systems."},{"key":"e_1_3_2_1_28_1","volume-title":"Automated Multi-objective Control for Self-adaptive Software Design. In Joint Meeting on Foundations of Software Engineering.","author":"Filieri Antonio","year":"2015","unstructured":"Antonio Filieri, Henry Hoffmann, and Martina Maggio. 2015. Automated Multi-objective Control for Self-adaptive Software Design. In Joint Meeting on Foundations of Software Engineering."},{"key":"e_1_3_2_1_29_1","volume-title":"http:\/\/www.gigabyte.us\/Motherboard\/GA-AX370-Gaming-5-rev-10#kf. Accessed","author":"GIGA-BYTE Technology Co.","year":"2019","unstructured":"GIGA-BYTE Technology Co., Ltd. 2019. GIGABYTE. http:\/\/www.gigabyte.us\/Motherboard\/GA-AX370-Gaming-5-rev-10#kf. Accessed: 2019."},{"key":"e_1_3_2_1_30_1","unstructured":"GlobeNewswire. 2017. AMD Delivers Semi-Custom Graphics Chip For New Intel Processor. http:\/\/www.nasdaq.com\/press-release\/amd-delivers-semicustom-graphics-chip-for-new-intel-processor-20171106-00859."},{"key":"e_1_3_2_1_31_1","volume-title":"Chai: Collaborative Heterogeneous Applications for Integrated-architectures. In IEEE International Symposium on Performance Analysis of Systems and Software.","author":"G\u00f3mez-Luna Juan","year":"2017","unstructured":"Juan G\u00f3mez-Luna, Izzat El Hajj, Victor Chang, Li-Wen Garcia-Flores, Simon Garcia de Gonzalo, Thomas Jablin, Antonio J Pena, and Wen-mei Hwu. 2017. Chai: Collaborative Heterogeneous Applications for Integrated-architectures. In IEEE International Symposium on Performance Analysis of Systems and Software."},{"key":"e_1_3_2_1_32_1","volume-title":"Konstantinov","author":"Gu Da-Wei","year":"2013","unstructured":"Da-Wei Gu, Petko H. Petkov, and Mihail M. Konstantinov. 2013. Robust Control Design with MATLAB (2nd ed.). Springer."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2463275"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2661430"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2007.48"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.8"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2012.7476478"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2742854.2742885"},{"key":"e_1_3_2_1_39_1","volume-title":"Formal Energy Management of Chip Multiprocessors. In International Symposium on Low Power Electronics and Design.","author":"Juang Philo","unstructured":"Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Martonosi, and Douglas W. Clark. 2005. Coordinated, Distributed, Formal Energy Management of Chip Multiprocessors. In International Symposium on Low Power Electronics and Design."},{"key":"e_1_3_2_1_40_1","volume-title":"AUDIT: Stress Testing the Automatic Way. In International Symposium on Microarchitecture. IEEE Computer Society, 212--223","author":"Kim Youngtaek","unstructured":"Youngtaek Kim, Lizy Kurian John, Sanjay Pant, Srilatha Manne, Michael Schulte, W. Lloyd Bircher, and Madhu S. Sibi Govindan. 2012. AUDIT: Stress Testing the Automatic Way. In International Symposium on Microarchitecture. IEEE Computer Society, 212--223."},{"key":"e_1_3_2_1_41_1","volume-title":"Design Automation Conference.","author":"Lefurgy Charles","year":"2013","unstructured":"Charles Lefurgy. 2013. Avoiding Core Meltdown! - Adaptive Techniques for Power and Thermal Management of Multi-Core Processors. https:\/\/researcher.watson.ibm.com\/researcher\/files\/us-lefurgy\/DAC2013_Lefurgy_v6.pdf. Tutorial, Design Automation Conference."},{"key":"e_1_3_2_1_42_1","volume-title":"Performance Directed Energy Management for Main Memory and Disks. In International Conference on Architectural Support for Programming Languages and Operating Systems.","author":"Li Xiaodong","year":"2004","unstructured":"Xiaodong Li, Zhenmin Li, Francis David, Pin Zhou, Yuanyuan Zhou, Sarita Adve, and Sanjeev Kumar. 2004. Performance Directed Energy Management for Main Memory and Disks. In International Conference on Architectural Support for Programming Languages and Operating Systems."},{"key":"e_1_3_2_1_43_1","volume-title":"System Identification: Theory for the User (2 ed.)","author":"Ljung Lennart","year":"1999","unstructured":"Lennart Ljung. 1999. System Identification: Theory for the User (2 ed.). Prentice Hall PTR, Upper Saddle River, NJ, USA."},{"key":"e_1_3_2_1_44_1","volume-title":"Automated Control of Multiple Software Goals Using Multiple Actuators. In Joint Meeting on Foundations of Software Engineering.","author":"Maggio Martina","year":"2017","unstructured":"Martina Maggio, Alessandro Vittorio Papadopoulos, Antonio Filieri, and Henry Hoffmann. 2017. Automated Control of Multiple Software Goals Using Multiple Actuators. In Joint Meeting on Foundations of Software Engineering."},{"key":"e_1_3_2_1_45_1","volume-title":"High Bandwidth Packaging Interconnect. In IEEE Electronic Components and Technology Conference.","author":"Mahajan Ravi","year":"2016","unstructured":"Ravi Mahajan, Robert Sankman, Neha Patel, Dae-Woo Kim, Kemal Aygun, Zhiguo Qian, Yidnekachew Mekonnen, Islam Salama, Sujit Sharan, Deepti Iyengar, and Debendra Mallik. 2016. Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect. In IEEE Electronic Components and Technology Conference."},{"key":"e_1_3_2_1_46_1","volume-title":"Dynamic GPGPU Power Management Using Adaptive Model Predictive Control. In International Symposium on High Performance Computer Architecture.","author":"Majumdar Abhinandan","unstructured":"Abhinandan Majumdar, Leonardo Piga, Indrani Paul, Joseph L. Greathouse, Wei Huang, and David H. Albonesi. 2017. Dynamic GPGPU Power Management Using Adaptive Model Predictive Control. In International Symposium on High Performance Computer Architecture."},{"key":"e_1_3_2_1_47_1","unstructured":"Marvell Corporation. 2019. MoChi Architecture. http:\/\/www.marvell.com\/architecture\/mochi\/."},{"key":"e_1_3_2_1_48_1","volume-title":"Fink","author":"Mathews John H.","year":"2006","unstructured":"John H. Mathews and Kurtis D. Fink. 2006. Numerical Methods Using MATLAB. Pearson Education, Limited. https:\/\/books.google.com\/books?id=-DpDPgAACAAJ"},{"key":"e_1_3_2_1_49_1","volume-title":"MSI Graphics Cards. https:\/\/www.msi.com\/Graphics-card\/Radeon-RX-580-8G. Accessed","author":"Micro-Star Int'l Co.","year":"2019","unstructured":"Micro-Star Int'l Co.,Ltd. 2019. MSI Graphics Cards. https:\/\/www.msi.com\/Graphics-card\/Radeon-RX-580-8G. Accessed: 2019."},{"key":"e_1_3_2_1_50_1","volume-title":"CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors. In International Conference for High Performance Computing, Networking, Storage and Analysis.","author":"Mishra Asit K.","unstructured":"Asit K. Mishra, Shekhard Srikantaiah, Mahmut Kandemir, and Chita R. Das. 2010. CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors. In International Conference for High Performance Computing, Networking, Storage and Analysis."},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173184"},{"key":"e_1_3_2_1_52_1","unstructured":"Kenneth Mitchell and Elliot Kim. 2017. Optimizing for AMD Ryzen CPU. http:\/\/32ipi028l5q82yhj72224m8j.wpengine.netdna-cdn.com\/wp-content\/uploads\/2017\/03\/GDC2017-Optimizing-For-AMD-Ryzen.pdf. Accessed: 2019."},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2464688"},{"key":"e_1_3_2_1_54_1","volume-title":"Hierarchical Power Management for Asymmetric Multi-core in Dark Silicon Era. In Design Automation Conference.","author":"Muthukaruppan Thannirmalai Somu","year":"2013","unstructured":"Thannirmalai Somu Muthukaruppan, Mihai Pricopi, Vanchinathan Venkataramani, Tulika Mitra, and Sanjay Vishin. 2013. Hierarchical Power Management for Asymmetric Multi-core in Dark Silicon Era. In Design Automation Conference."},{"key":"e_1_3_2_1_55_1","volume-title":"Common Heterogeneous Integration and IP Reuse Strategies (CHIPS). https:\/\/www.darpa.mil\/program\/common-heterogeneous-integration-and-ip-reuse-strategies","author":"Olofsson Andreas","unstructured":"Andreas Olofsson. 2016. Common Heterogeneous Integration and IP Reuse Strategies (CHIPS). https:\/\/www.darpa.mil\/program\/common-heterogeneous-integration-and-ip-reuse-strategies. Defense Advanced Research Projects Agency."},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750404"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485947"},{"key":"e_1_3_2_1_58_1","volume-title":"Coordinated Energy Management in Heterogeneous Processors. In International Conference for High Performance Computing, Networking, Storage and Analysis.","author":"Paul Indrani","year":"2013","unstructured":"Indrani Paul, Vignesh Ravi, Srilatha Manne, Manish Arora, and Sudhakar Yalamanchili. 2013. Coordinated Energy Management in Heterogeneous Processors. In International Conference for High Performance Computing, Networking, Storage and Analysis."},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.63"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00049"},{"key":"e_1_3_2_1_61_1","unstructured":"Michael A. Prospero. 2014. AMD Announces New Low-Power APUs for Tablets and Notebooks. https:\/\/www.laptopmag.com\/articles\/amd-mullins-beema-apu."},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/1346281.1346289"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173199"},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/CCA.2015.7320717"},{"key":"e_1_3_2_1_65_1","volume-title":"Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices. In International Symposium on High Performance Computer Architecture.","author":"Rao Karthik","year":"2017","unstructured":"Karthik Rao, Jun Wang, Sudhakar Yalamanchili, Yorai Wardi, and Handong Ye. 2017. Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices. In International Symposium on High Performance Computer Architecture."},{"key":"e_1_3_2_1_66_1","unstructured":"Todd Rosedahl. 2014. OCC Firmware Code is Now Open Source. https:\/\/openpowerfoundation.org\/occ-firmware-code-is-now-open-source\/. Code: https:\/\/github.com\/open-power\/docs\/blob\/master\/occ\/OCC_overview.md."},{"key":"e_1_3_2_1_67_1","volume-title":"Power\/Performance Controlling Techniques in OpenPOWER","author":"Rosedahl Todd","unstructured":"Todd Rosedahl, Martha Broyles, Charles Lefurgy, Bjorn Christensen, and Wu Feng. 2017. Power\/Performance Controlling Techniques in OpenPOWER. In High Performance Computing, Julian M. Kunkel, Rio Yokota, Michela Taufer, and John Shalf (Eds.). Springer International Publishing, 275--289."},{"key":"e_1_3_2_1_68_1","unstructured":"Efraim Rotem. 2015. Intel Architecture Code Name Skylake Deep Dive: A New Architecture to Manage Power Performance and Energy Efficiency. Intel Developer Forum."},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.12"},{"key":"e_1_3_2_1_70_1","volume-title":"GRAPE: Minimizing Energy for GPU Applications with Performance Requirements. In International Symposium on Microarchitecture.","author":"Santriaji Muhammad Husni","year":"2016","unstructured":"Muhammad Husni Santriaji and Henry Hoffmann. 2016. GRAPE: Minimizing Energy for GPU Applications with Performance Requirements. In International Symposium on Microarchitecture."},{"key":"e_1_3_2_1_71_1","volume-title":"Keep It SIMPLEX: Satisfying Multiple Goals with Guarantees in Control-based Self-adaptive Systems. In ACM SIGSOFT International Symposium on Foundations of Software Engineering. 229--241","author":"Shevtsov Stepan","year":"2016","unstructured":"Stepan Shevtsov and Danny Weyns. 2016. Keep It SIMPLEX: Satisfying Multiple Goals with Guarantees in Control-based Self-adaptive Systems. In ACM SIGSOFT International Symposium on Foundations of Software Engineering. 229--241."},{"key":"e_1_3_2_1_72_1","first-page":"1","article-title":"Advanced Features in IBM POWER8 systems","volume":"59","author":"Sinharoy Balaram","year":"2015","unstructured":"Balaram Sinharoy, Randy Swanberg, Naresh Nayar, Bruce G. Mealey, Jeff Stuecheli, Berni Schiefer, Jens Leenstra, Joefon Jann, Philipp Oehler, David Levitan, Susan Eisen, Dean Sanner, Thomas Pflueger, Cedric Lichtenau, William E. Hall, and Tim Block. 2015. Advanced Features in IBM POWER8 systems. IBM Jour. Res. Dev. 59, 1 (Jan. 2015), 1:1--1:18.","journal-title":"IBM Jour. Res. Dev."},{"key":"e_1_3_2_1_73_1","volume-title":"Multivariable Feedback Control: Analysis and Design","author":"Skogestad Sigurd","unstructured":"Sigurd Skogestad and Ian Postlethwaite. 2005. Multivariable Feedback Control: Analysis and Design. John Wiley & Sons."},{"key":"e_1_3_2_1_74_1","unstructured":"SKYMTL. 2014. AMD Mullins & Beema Mobile APUs Preview. amd-mullins-beema-mobile-apus-preview.html."},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.17"},{"key":"e_1_3_2_1_76_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2016.106"},{"key":"e_1_3_2_1_77_1","volume-title":"The Future of IC Design Innovation. In International Solid-State Circuits Conference.","author":"Sutardja Sehat","year":"2015","unstructured":"Sehat Sutardja. 2015. The Future of IC Design Innovation. In International Solid-State Circuits Conference."},{"key":"e_1_3_2_1_78_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540727"},{"key":"e_1_3_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.42"},{"key":"e_1_3_2_1_80_1","volume-title":"Workload and Power Budget Partitioning for Single-chip Heterogeneous Processors. In International Conference on Parallel Architectures and Compilation Techniques.","author":"Wang Hao","year":"2012","unstructured":"Hao Wang, Vijay Sathish, Ripudaman Singh, Michael J. Schulte, and Nam Sung Kim. 2012. Workload and Power Budget Partitioning for Single-chip Heterogeneous Processors. In International Conference on Parallel Architectures and Compilation Techniques."},{"key":"e_1_3_2_1_81_1","unstructured":"Xin Wang. 2017. Intelligent Power Allocation: Maximize performance in the thermal envelope. ARM White Paper."},{"key":"e_1_3_2_1_82_1","volume-title":"International Symposium on High Performance Computer Architecture.","author":"Wang Xiaodong","unstructured":"Xiaodong Wang and Jos\u00e9 F. Mart\u00ednez. 2015. XChange: A Market-based Approach to Scalable Dynamic Multi-resource Allocation in Multicore Architectures. In International Symposium on High Performance Computer Architecture."},{"key":"e_1_3_2_1_83_1","volume-title":"International Conference on Architectural Support for Programming Languages and Operating Systems.","author":"Wang Xiaodong","unstructured":"Xiaodong Wang and Jos\u00e9 F. Mart\u00ednez. 2016. ReBudget: Trading Off Efficiency vs. Fairness in Market-Based Multicore Resource Allocation via Runtime Budget Reassignment. In International Conference on Architectural Support for Programming Languages and Operating Systems."},{"key":"e_1_3_2_1_84_1","volume-title":"Temperature-constrained Power Control for Chip Multiprocessors with Online Model Estimation. In International Symposium on Computer Architecture.","author":"Wang Yefu","year":"2009","unstructured":"Yefu Wang, Kai Ma, and Xiaorui Wang. 2009. Temperature-constrained Power Control for Chip Multiprocessors with Online Model Estimation. In International Symposium on Computer Architecture."},{"key":"e_1_3_2_1_85_1","volume-title":"Formal Online Methods for Voltage\/Frequency Control in Multiple Clock Domain Microprocessors. In International Conference on Architectural Support for Programming Languages and Operating Systems.","author":"Wu Qiang","unstructured":"Qiang Wu, Philo Juang, Margaret Martonosi, and Douglas W. Clark. 2004. Formal Online Methods for Voltage\/Frequency Control in Multiple Clock Domain Microprocessors. In International Conference on Architectural Support for Programming Languages and Operating Systems."},{"key":"e_1_3_2_1_86_1","volume-title":"Modular Routing Design for Chiplet-Based Systems. In International Symposium on Computer Architecture.","author":"Yin Jieming","unstructured":"Jieming Yin, Zhifeng Lin, Onur Kayiran, Matthew Poremba, Muhammad Shoaib Bin Altaf, Natahlie Enright Jerger, and Gbriel H. Loh. 2018. Modular Routing Design for Chiplet-Based Systems. In International Symposium on Computer Architecture."}],"event":{"name":"MICRO '52: The 52nd Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Columbus OH USA","acronym":"MICRO '52","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE CS"]},"container-title":["Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3352460.3358285","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3352460.3358285","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3352460.3358285","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,29]],"date-time":"2025-07-29T22:26:12Z","timestamp":1753827972000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3352460.3358285"}},"subtitle":["Integrated Control of Heterogeneous Computers"],"short-title":[],"issued":{"date-parts":[[2019,10,12]]},"references-count":86,"alternative-id":["10.1145\/3352460.3358285","10.1145\/3352460"],"URL":"https:\/\/doi.org\/10.1145\/3352460.3358285","relation":{},"subject":[],"published":{"date-parts":[[2019,10,12]]},"assertion":[{"value":"2019-10-12","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}