{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:28:28Z","timestamp":1750220908381,"version":"3.41.0"},"reference-count":41,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2019,9,9]],"date-time":"2019-09-09T00:00:00Z","timestamp":1567987200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2019,12,31]]},"abstract":"<jats:p>\n            In earlier technology nodes, FPGAs had low power consumption compared to other compute chips such as CPUs and GPUs. However, in the 14nm technology node, FPGAs are consuming unprecedented power in the 100+W range, making power consumption a pressing concern. To reduce FPGA power consumption, several researchers have proposed deploying dynamic voltage scaling. While the previously proposed solutions show promising results, they have difficulty guaranteeing safe operation at reduced voltages for applications that use the FPGA hard blocks. In this work, we present the first DVS solution that is able to fully handle FPGA applications that use BRAMs. Our solution not only robustly tests the soft logic component of the application but also tests all components connected to the BRAMs. We extend a previously proposed CAD tool, FRoC, to automatically generate calibration bitstreams that are used to measure the application\u2019s critical path delays on silicon. The calibration bitstreams also include testers that ensure all used SRAM cells operate safely while scaling V\n            <jats:sub>dd<\/jats:sub>\n            . We experimentally show that using our DVS solution we can save 32% of the total power consumed by a discrete Fourier transform application running with the fixed nominal supply voltage and clocked at the F\n            <jats:sub>max<\/jats:sub>\n            reported by static timing analysis.\n          <\/jats:p>","DOI":"10.1145\/3354188","type":"journal-article","created":{"date-parts":[[2019,9,9]],"date-time":"2019-09-09T12:10:26Z","timestamp":1568031026000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["FRoC 2.0"],"prefix":"10.1145","volume":"12","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2696-3086","authenticated-orcid":false,"given":"Ibrahim","family":"Ahmed","sequence":"first","affiliation":[{"name":"University of Toronto, Toronto, Ontario"}]},{"given":"Shuze","family":"Zhao","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, Ontario"}]},{"given":"James","family":"Meijers","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, Ontario"}]},{"given":"Olivier","family":"Trescases","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, Ontario"}]},{"given":"Vaughn","family":"Betz","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, Ontario"}]}],"member":"320","published-online":{"date-parts":[[2019,9,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"e_1_2_1_2_1","doi-asserted-by":"crossref","unstructured":"A. Putnam A. M. Caulfield E. S. Chung D. Chiou K. Constantinides J. Demme H. Esmaeilzadeh J. Fowers G. P. Gopal J. Gray M. Haselman S. Hauck S. Heil A. Hormati J. Y. Kim S. Lanka J. Larus E. Peterson S. Pope A. Smith J. Thong P. Y. Xiao and D. Burger. 2014. A reconfigurable fabric for accelerating large-scale datacenter services. In ISCA.   A. Putnam A. M. Caulfield E. S. Chung D. Chiou K. Constantinides J. Demme H. Esmaeilzadeh J. Fowers G. P. Gopal J. Gray M. Haselman S. Hauck S. Heil A. Hormati J. Y. Kim S. Lanka J. Larus E. Peterson S. Pope A. Smith J. Thong P. Y. Xiao and D. Burger. 2014. A reconfigurable fabric for accelerating large-scale datacenter services. In ISCA.","DOI":"10.1109\/ISCA.2014.6853195"},{"volume-title":"List of CPU Power Dissipation Figures. Retrieved","year":"2019","key":"e_1_2_1_3_1","unstructured":"Wikipedia. 2019. List of CPU Power Dissipation Figures. Retrieved May 2, 2019 https:\/\/en.wikipedia.org\/wiki\/List_of_CPU_power_dissipation_figures. Wikipedia. 2019. List of CPU Power Dissipation Figures. Retrieved May 2, 2019 https:\/\/en.wikipedia.org\/wiki\/List_of_CPU_power_dissipation_figures."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117203"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2513683.2513689"},{"key":"e_1_2_1_6_1","doi-asserted-by":"crossref","unstructured":"S. Zhao I. Ahmed C. Lamoureux A. Lotfi V. Betz and O. Trescases. 2016. A universal self-calibrating dynamic voltage and frequency scaling (DVFS) scheme with thermal compensation for energy savings in FPGAs. In APEC.  S. Zhao I. Ahmed C. Lamoureux A. Lotfi V. Betz and O. Trescases. 2016. A universal self-calibrating dynamic voltage and frequency scaling (DVFS) scheme with thermal compensation for energy savings in FPGAs. In APEC.","DOI":"10.1109\/APEC.2016.7468125"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554784"},{"key":"e_1_2_1_8_1","unstructured":"C. T. Chow L. S. M. Tsui P. H. W. Leong W. Luk and S. J. E. Wilton. 2005. Dynamic voltage scaling for commercial FPGAs. In FPT.  C. T. Chow L. S. M. Tsui P. H. W. Leong W. Luk and S. J. E. Wilton. 2005. Dynamic voltage scaling for commercial FPGAs. In FPT."},{"key":"e_1_2_1_9_1","doi-asserted-by":"crossref","unstructured":"I. Ahmed S. Zhao O. Trescases and V. Betz. 2016. Measure twice and cut once: Robust dynamic voltage scaling for FPGAs. In FPL.  I. Ahmed S. Zhao O. Trescases and V. Betz. 2016. Measure twice and cut once: Robust dynamic voltage scaling for FPGAs. In FPL.","DOI":"10.1109\/FPL.2016.7577342"},{"key":"e_1_2_1_10_1","doi-asserted-by":"crossref","unstructured":"S. Zhao I. Ahmed A. Khakpour V. Betz and O. Trescases. 2017. A robust dynamic voltage scaling scheme for FPGAs with IR drop compensation. In APEC.  S. Zhao I. Ahmed A. Khakpour V. Betz and O. Trescases. 2017. A robust dynamic voltage scaling scheme for FPGAs with IR drop compensation. In APEC.","DOI":"10.1109\/APEC.2017.7931114"},{"key":"e_1_2_1_11_1","doi-asserted-by":"crossref","unstructured":"V. R. Devanathan A. Hales S. Kale and D. Sonkar. 2010. Towards effective and compression-friendly test of memory interface logic. In ITC.  V. R. Devanathan A. Hales S. Kale and D. Sonkar. 2010. Towards effective and compression-friendly test of memory interface logic. In ITC.","DOI":"10.1109\/TEST.2010.5699212"},{"key":"e_1_2_1_12_1","unstructured":"L. C. Chen P. Dickinson P. Mantri M. Gala P. Dahlgren S. Bhattacharya O. Caty K. Woodling T. Ziaja D. Curwen W. Yee E. Su G. Gu and T. Nguyen. 2008. Transition test on UltraSPARC-T2 microprocessor. In ITC.  L. C. Chen P. Dickinson P. Mantri M. Gala P. Dahlgren S. Bhattacharya O. Caty K. Woodling T. Ziaja D. Curwen W. Yee E. Su G. Gu and T. Nguyen. 2008. Transition test on UltraSPARC-T2 microprocessor. In ITC."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MTV.2004.17"},{"key":"e_1_2_1_14_1","doi-asserted-by":"crossref","unstructured":"I. Ahmed S. Zhao J. Meijers O. Trescases and V. Betz. 2018. Automatic BRAM testing for robust dynamic voltage scaling for FPGAs. In FPL.  I. Ahmed S. Zhao J. Meijers O. Trescases and V. Betz. 2018. Automatic BRAM testing for robust dynamic voltage scaling for FPGAs. In FPL.","DOI":"10.1109\/FPL.2018.00020"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155622"},{"key":"e_1_2_1_16_1","doi-asserted-by":"crossref","unstructured":"A. Drake R. Senger H. Deogun G. Carpenter S. Ghiasi T. Nguyen N. James M. Floyd and V. Pokala. 2007. A distributed critical-path timing monitor for a 65nm high-performance microprocessor. In ISSCC.  A. Drake R. Senger H. Deogun G. Carpenter S. Ghiasi T. Nguyen N. James M. Floyd and V. Pokala. 2007. A distributed critical-path timing monitor for a 65nm high-performance microprocessor. In ISSCC.","DOI":"10.1109\/ISSCC.2007.373462"},{"key":"e_1_2_1_17_1","doi-asserted-by":"crossref","unstructured":"B. Bowhill B. Stackhouse N. Nassif Z. Yang A. Raghavan C. Morganti C. Houghton D. Krueger O. Franza J. Desai J. Crop D. Bradley C. Bostak S. Bhimji and M. Becker. 2015. The Xeon processor E5-2600 v3: A 22nm 18-core product family. In ISSCC.  B. Bowhill B. Stackhouse N. Nassif Z. Yang A. Raghavan C. Morganti C. Houghton D. Krueger O. Franza J. Desai J. Crop D. Bradley C. Bostak S. Bhimji and M. Becker. 2015. The Xeon processor E5-2600 v3: A 22nm 18-core product family. In ISSCC.","DOI":"10.1109\/ISSCC.2015.7062934"},{"key":"e_1_2_1_18_1","first-page":"1","article-title":"The Xeon processor E5-2600 v3: A 22nm 18-core product family","volume":"51","author":"Bowhill B.","year":"2016","unstructured":"B. Bowhill , B. Stackhouse , N. Nassif , Z. Yang , A. Raghavan , O. Mendoza , C. Morganti , C. Houghton , D. Krueger , O. Franza , J. Desai , J. Crop , B. Brock , D. Bradley , C. Bostak , S. Bhimji , and M. Becker . 2016 . The Xeon processor E5-2600 v3: A 22nm 18-core product family . IEEE. Solid-State Circ. 51 , 1 (Jan. 2016), 92--104. B. Bowhill, B. Stackhouse, N. Nassif, Z. Yang, A. Raghavan, O. Mendoza, C. Morganti, C. Houghton, D. Krueger, O. Franza, J. Desai, J. Crop, B. Brock, D. Bradley, C. Bostak, S. Bhimji, and M. Becker. 2016. The Xeon processor E5-2600 v3: A 22nm 18-core product family. IEEE. Solid-State Circ. 51, 1 (Jan. 2016), 92--104.","journal-title":"IEEE. Solid-State Circ."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2392616.2392618"},{"key":"e_1_2_1_20_1","volume-title":"Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors. Microprocess. Microsyst. 51 (June","author":"Nunez-Yanez Jose","year":"2017","unstructured":"Jose Nunez-Yanez . 2017. Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors. Microprocess. Microsyst. 51 (June 2017 ), 227--238. Jose Nunez-Yanez. 2017. Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors. Microprocess. Microsyst. 51 (June 2017), 227--238."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021731"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382534"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.207"},{"key":"e_1_2_1_25_1","doi-asserted-by":"crossref","unstructured":"E. Stott J. M. Levine P. Y. K. Cheung and N. Kapre. 2014. Timing fault detection in FPGA-based circuits. In FCCM.   E. Stott J. M. Levine P. Y. K. Cheung and N. Kapre. 2014. Timing fault detection in FPGA-based circuits. In FCCM.","DOI":"10.1109\/FCCM.2014.32"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882503"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855955"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1534916.1534920"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2013.63"},{"key":"e_1_2_1_30_1","doi-asserted-by":"crossref","unstructured":"C. Chiasson and V. Betz. 2013. Should FPGAs abandon the pass-gate? In FPL.  C. Chiasson and V. Betz. 2013. Should FPGAs abandon the pass-gate? In FPL.","DOI":"10.1109\/FPL.2013.6645511"},{"key":"e_1_2_1_31_1","unstructured":"Altera. 2014. Cyclone IV Device Handbook.  Altera. 2014. Cyclone IV Device Handbook."},{"key":"e_1_2_1_33_1","doi-asserted-by":"crossref","unstructured":"S. Zhao I. Ahmed C. Lamoureux A. Lotfi V. Betz and O. Trescases. 2016. A universal self-calibrating dynamic voltage and frequency scaling (DVFS) scheme with thermal compensation for energy savings in FPGAs. In APEC.  S. Zhao I. Ahmed C. Lamoureux A. Lotfi V. Betz and O. Trescases. 2016. A universal self-calibrating dynamic voltage and frequency scaling (DVFS) scheme with thermal compensation for energy savings in FPGAs. In APEC.","DOI":"10.1109\/APEC.2016.7468125"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145710"},{"key":"e_1_2_1_35_1","doi-asserted-by":"crossref","unstructured":"Z. Guan J. S. J. Wong S. Chaudhuri G. Constantinides and P. Y. K. Cheung. 2012. A two-stage variation-aware placement method for FPGAs exploiting variation maps classification. In FPL.  Z. Guan J. S. J. Wong S. Chaudhuri G. Constantinides and P. Y. K. Cheung. 2012. A two-stage variation-aware placement method for FPGAs exploiting variation maps classification. In FPL.","DOI":"10.1109\/FPL.2012.6339269"},{"key":"e_1_2_1_36_1","doi-asserted-by":"crossref","unstructured":"Yuko Hara Hiroyuki Tomiyama Shinya Honda Hiroaki Takada and Katsuya Ishii. 2008. CHStone: A benchmark program suite for practical C-based high-level synthesis. In ISCAS.  Yuko Hara Hiroyuki Tomiyama Shinya Honda Hiroaki Takada and Katsuya Ishii. 2008. CHStone: A benchmark program suite for practical C-based high-level synthesis. In ISCAS.","DOI":"10.1109\/ISCAS.2008.4541637"},{"key":"e_1_2_1_37_1","volume-title":"Titan: Enabling large and complex benchmarks in academic CAD. In FPL.","author":"Murray K. E.","year":"2013","unstructured":"K. E. Murray , S. Whitty , S. Liu , J. Luu , and V. Betz . 2013 . Titan: Enabling large and complex benchmarks in academic CAD. In FPL. K. E. Murray, S. Whitty, S. Liu, J. Luu, and V. Betz. 2013. Titan: Enabling large and complex benchmarks in academic CAD. In FPL."},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2159542.2159547"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228588"},{"key":"e_1_2_1_40_1","unstructured":"Jian Liang R. Tessier and D. Goeckel. 2004. A dynamically-reconfigurable power-efficient turbo decoder. In FCCM.   Jian Liang R. Tessier and D. Goeckel. 2004. A dynamically-reconfigurable power-efficient turbo decoder. In FCCM."},{"key":"e_1_2_1_41_1","doi-asserted-by":"crossref","unstructured":"I. Ahmed S. Zhao O. Trescases and V. Betz. 2017. Find the real speed limit: FPGA CAD for chip-specific application delay measurement. In FPL.  I. Ahmed S. Zhao O. Trescases and V. Betz. 2017. Find the real speed limit: FPGA CAD for chip-specific application delay measurement. In FPL.","DOI":"10.23919\/FPL.2017.8056819"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2017.2775448"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3354188","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3354188","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:44:56Z","timestamp":1750203896000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3354188"}},"subtitle":["Automatic BRAM and Logic Testing to Enable Dynamic Voltage Scaling for FPGA Applications"],"short-title":[],"issued":{"date-parts":[[2019,9,9]]},"references-count":41,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2019,12,31]]}},"alternative-id":["10.1145\/3354188"],"URL":"https:\/\/doi.org\/10.1145\/3354188","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2019,9,9]]},"assertion":[{"value":"2018-12-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-09-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}