{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:28:25Z","timestamp":1750220905657,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":26,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,11,6]],"date-time":"2019-11-06T00:00:00Z","timestamp":1572998400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,11,6]]},"DOI":"10.1145\/3356401.3356416","type":"proceedings-article","created":{"date-parts":[[2019,11,5]],"date-time":"2019-11-05T18:56:15Z","timestamp":1572980175000},"page":"61-69","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip"],"prefix":"10.1145","author":[{"given":"Amaury","family":"Graillat","sequence":"first","affiliation":[{"name":"Univ. Grenoble Alpes, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Claire","family":"Maiza","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthieu","family":"Moy","sequence":"additional","affiliation":[{"name":"Univ Lyon, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pascal","family":"Raymond","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Beno\u00eet Dupont","family":"de Dinechin","sequence":"additional","affiliation":[{"name":"Kalray S.A, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,11,6]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2834848.2834862"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/WFCS.2016.7496535"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-16256-5_6"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2016.14"},{"key":"e_1_3_2_1_5_1","volume-title":"SCADE: Synchronous design and validation of embedded control software. In Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems","author":"Berry G\u00e9rard","year":"2007","unstructured":"G\u00e9rard Berry . 2007 . SCADE: Synchronous design and validation of embedded control software. In Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems . Springer , 19--33. G\u00e9rard Berry. 2007. SCADE: Synchronous design and validation of embedded control software. In Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems. Springer, 19--33."},{"key":"e_1_3_2_1_6_1","volume-title":"ERTS 2018-9th European Congress on Embedded Real Time Software and Systems.","author":"Boyer Marc","year":"2018","unstructured":"Marc Boyer , Beno\u00eet Dupont de Dinechin , Amaury Graillat , and Lionel Havet . 2018 . Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor . In ERTS 2018-9th European Congress on Embedded Real Time Software and Systems. Marc Boyer, Beno\u00eet Dupont de Dinechin, Amaury Graillat, and Lionel Havet. 2018. Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor. In ERTS 2018-9th European Congress on Embedded Real Time Software and Systems."},{"key":"e_1_3_2_1_7_1","volume-title":"Forum on specification & Design Languages (FDL).","author":"Cola\u00e7o Jean-Louis","year":"1960","unstructured":"Jean-Louis Cola\u00e7o , Bruno Pagano , C\u00e9dric Pasteur , and Marc Pouzet . 2018. Scade 6: from a Kahn Semantics to a Kahn Implementation for Multicore . In Forum on specification & Design Languages (FDL). Munich, Germany . https:\/\/hal.archives-ouvertes.fr\/hal-0 1960 410. Jean-Louis Cola\u00e7o, Bruno Pagano, C\u00e9dric Pasteur, and Marc Pouzet. 2018. Scade 6: from a Kahn Semantics to a Kahn Implementation for Multicore. In Forum on specification & Design Languages (FDL). Munich, Germany. https:\/\/hal.archives-ouvertes.fr\/hal-01960410."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/3073763.3073770"},{"key":"e_1_3_2_1_9_1","volume-title":"Proceedings of the Conference on Design, Automation & Test in Europe (DATE '14)","author":"de Dinechin Beno\u00eet Dupont","year":"2014","unstructured":"Beno\u00eet Dupont de Dinechin , Duco van Amstel , Marc Poulhi\u00e8s , and Guillaume Lager . 2014 . Time-critical Computing on a Single-chip Massively Parallel Processor . In Proceedings of the Conference on Design, Automation & Test in Europe (DATE '14) . European Design and Automation Association, 3001 Leuven, Belgium, Belgium, Article 97, 6 pages. http:\/\/dl.acm.org\/citation.cfm?id=2616606.2616725 Beno\u00eet Dupont de Dinechin, Duco van Amstel, Marc Poulhi\u00e8s, and Guillaume Lager. 2014. Time-critical Computing on a Single-chip Massively Parallel Processor. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE '14). European Design and Automation Association, 3001 Leuven, Belgium, Belgium, Article 97, 6 pages. http:\/\/dl.acm.org\/citation.cfm?id=2616606.2616725"},{"key":"e_1_3_2_1_10_1","volume-title":"ERTS 2014-7th European Congress on Embedded Real Time Software and Systems.","author":"Durrieu Guy","year":"2014","unstructured":"Guy Durrieu , Madeleine Faugere , Sylvain Girbal , Daniel Gracia P\u00e9rez , Claire Pagetti , and Wolfgang Puffitsch . 2014 . Predictable Flight Management System Implementation on a Multicore Processor . In ERTS 2014-7th European Congress on Embedded Real Time Software and Systems. Guy Durrieu, Madeleine Faugere, Sylvain Girbal, Daniel Gracia P\u00e9rez, Claire Pagetti, and Wolfgang Puffitsch. 2014. Predictable Flight Management System Implementation on a Multicore Processor. In ERTS 2014-7th European Congress on Embedded Real Time Software and Systems."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2012.35"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2016.7402269"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-015-9227-y"},{"volume-title":"Parallel code generation of synchronous programs for a many-core architecture","author":"Graillat Amaury","key":"e_1_3_2_1_14_1","unstructured":"Amaury Graillat , Matthieu Moy , Pascal Raymond , and Beno\u00eet Dupont de Dinechin . 2018. Parallel code generation of synchronous programs for a many-core architecture . In DATE. IEEE , 1139--1142. Amaury Graillat, Matthieu Moy, Pascal Raymond, and Beno\u00eet Dupont de Dinechin. 2018. Parallel code generation of synchronous programs for a many-core architecture. In DATE. IEEE, 1139--1142."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342182"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.97300"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2623619"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2480741.2480755"},{"key":"e_1_3_2_1_20_1","unstructured":"The Mathworks. [n. d.]. Simulink: User's Guide.  The Mathworks. [n. d.]. Simulink: User's Guide."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2834848.2834854"},{"key":"e_1_3_2_1_22_1","volume-title":"A model based safety critical flow for the AURIX multi-core platform. Embedded Real-Time Software and Systems (ERTS'18)","author":"Pagano Bruno","year":"2018","unstructured":"Bruno Pagano , C\u00e9dric Pasteur , G\u00fcnther Siegel , and R Kn\u00ed\u017aek . 2018. A model based safety critical flow for the AURIX multi-core platform. Embedded Real-Time Software and Systems (ERTS'18) ( 2018 ). Bruno Pagano, C\u00e9dric Pasteur, G\u00fcnther Siegel, and R Kn\u00ed\u017aek. 2018. A model based safety critical flow for the AURIX multi-core platform. Embedded Real-Time Software and Systems (ERTS'18) (2018)."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6926012"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2997465.2997472"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/CODESISSS.2015.7331385"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-44878-7_13"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2014.10"}],"event":{"name":"RTNS 2019: 27th International Conference on Real-Time Networks and Systems","acronym":"RTNS 2019","location":"Toulouse France"},"container-title":["Proceedings of the 27th International Conference on Real-Time Networks and Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3356401.3356416","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3356401.3356416","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:44:52Z","timestamp":1750203892000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3356401.3356416"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11,6]]},"references-count":26,"alternative-id":["10.1145\/3356401.3356416","10.1145\/3356401"],"URL":"https:\/\/doi.org\/10.1145\/3356401.3356416","relation":{},"subject":[],"published":{"date-parts":[[2019,11,6]]},"assertion":[{"value":"2019-11-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}