{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,17]],"date-time":"2026-10-17T22:18:30Z","timestamp":1792275510187,"version":"4.4.0"},"reference-count":24,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2019,10,31]],"date-time":"2019-10-31T00:00:00Z","timestamp":1572480000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2019,12,31]]},"abstract":"<jats:p>High Level Synthesis is a set of methodologies aimed at generating hardware descriptions starting from specifications written in high-level languages. While these methodologies share different elements with traditional compilation flows, there are characteristics of the addressed problem which require ad hoc management. In particular, differently from most of the traditional compilation flows, the complexity and the execution time of the High Level Synthesis techniques are much less relevant than the quality of the produced results. For this reason, fixed-point analyses, as well as successive refinement optimizations, can be accepted, provided that they can improve the quality of the generated designs.<\/jats:p>\n          <jats:p>This article presents a design flow engine for the description and the execution of complex and customized synthesis flows. It supports dynamic addition of passes and dependencies, cyclic dependencies, and selective pass invalidation. Experimental results show the benefits of such type of design flows with respect to static linear design flows when applied to High Level Synthesis.<\/jats:p>","DOI":"10.1145\/3356475","type":"journal-article","created":{"date-parts":[[2019,10,31]],"date-time":"2019-10-31T12:23:34Z","timestamp":1572524614000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows"],"prefix":"10.1145","volume":"12","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0062-6049","authenticated-orcid":false,"given":"Marco","family":"Lattuada","sequence":"first","affiliation":[{"name":"Politecnico di Milano, Milano , Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Fabrizio","family":"Ferrandi","sequence":"additional","affiliation":[{"name":"Politecnico di Milano, Milano , Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,10,31]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2928270"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2514740"},{"key":"e_1_2_1_3_1","volume-title":"xpilot: A platform-based behavioral synthesis system. SRC TechCon 5","author":"Chen Deming","year":"2005","unstructured":"Deming Chen , Jason Cong , Yiping Fan , Guoling Han , Wei Jiang , and Zhiru Zhang . 2005. xpilot: A platform-based behavioral synthesis system. SRC TechCon 5 ( 2005 ). Deming Chen, Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, and Zhiru Zhang. 2005. xpilot: A platform-based behavioral synthesis system. SRC TechCon 5 (2005)."},{"key":"e_1_2_1_4_1","first-page":"4","article-title":"High-level synthesis for FPGAs: From prototyping to deployment","volume":"30","author":"Cong J.","year":"2011","unstructured":"J. Cong , Bin Liu , S. Neuendorffer , J. Noguera , K. Vissers , and Zhiru Zhang . 2011 . High-level synthesis for FPGAs: From prototyping to deployment . IEEE TCAD 30 , 4 (April 2011), 473--491. J. Cong, Bin Liu, S. Neuendorffer, J. Noguera, K. Vissers, and Zhiru Zhang. 2011. High-level synthesis for FPGAs: From prototyping to deployment. IEEE TCAD 30, 4 (April 2011), 473--491.","journal-title":"IEEE TCAD"},{"key":"e_1_2_1_5_1","volume-title":"Proceedings of the 25th International Workshop on Languages and Compilers for Parallel Computing (LCPC\u201912)","author":"Cong Jason","year":"2012","unstructured":"Jason Cong , Bin Liu , Raghu Prabhakar , and Peng Zhang . 2012 . A study on the impact of compiler optimizations on high-level synthesis . In Proceedings of the 25th International Workshop on Languages and Compilers for Parallel Computing (LCPC\u201912) , Revised Selected Papers. 143--157. DOI:https:\/\/doi.org\/10.1007\/978-3-642-37658-0_10 10.1007\/978-3-642-37658-0_10 Jason Cong, Bin Liu, Raghu Prabhakar, and Peng Zhang. 2012. A study on the impact of compiler optimizations on high-level synthesis. In Proceedings of the 25th International Workshop on Languages and Compilers for Parallel Computing (LCPC\u201912), Revised Selected Papers. 143--157. DOI:https:\/\/doi.org\/10.1007\/978-3-642-37658-0_10"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147025"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065910.1065921"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357111"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-010-0161-2"},{"key":"e_1_2_1_10_1","volume-title":"Retrieved on","author":"GNU","year":"2015","unstructured":"GNU GCC. 2015 . Plugin API . Retrieved on September 04, 2019 from https:\/\/gcc.gnu.org\/wiki\/GCC_Plugins. GNU GCC. 2015. Plugin API. Retrieved on September 04, 2019 from https:\/\/gcc.gnu.org\/wiki\/GCC_Plugins."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjjip.17.242"},{"key":"e_1_2_1_12_1","volume-title":"Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation","author":"Hauck Scott","year":"2007","unstructured":"Scott Hauck and Andre DeHon . 2007 . Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation . Morgan Kaufmann Publishers Inc ., San Francisco, CA. Scott Hauck and Andre DeHon. 2007. Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann Publishers Inc., San Francisco, CA."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2629547"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1071604.1071607"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/977395.977673"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/2840819.2840830"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"},{"key":"e_1_2_1_19_1","volume-title":"Proceedings of the 17th ACM SIGPLAN\/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES\u201916)","author":"Nobre Ricardo","unstructured":"Ricardo Nobre , Luiz G. A. Martins , and Jo\u00e3o M. P. Cardoso . 2016. A graph-based iterative compiler pass selection and phase ordering approach . In Proceedings of the 17th ACM SIGPLAN\/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES\u201916) . ACM, New York, NY, 21--30. DOI:https:\/\/doi.org\/10.1145\/2907950.2907959 10.1145\/2907950.2907959 Ricardo Nobre, Luiz G. A. Martins, and Jo\u00e3o M. P. Cardoso. 2016. A graph-based iterative compiler pass selection and phase ordering approach. In Proceedings of the 17th ACM SIGPLAN\/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES\u201916). ACM, New York, NY, 21--30. DOI:https:\/\/doi.org\/10.1145\/2907950.2907959"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645550"},{"key":"e_1_2_1_21_1","volume-title":"GNU GCC Speedup Areas. Retrieved on","author":"Richard","year":"2019","unstructured":"Richard M. Stallman and the GCC Developer Community. 2015 . GNU GCC Speedup Areas. Retrieved on September 04, 2019 from https:\/\/gcc.gnu.org\/wiki\/Speedup_areas. Richard M. Stallman and the GCC Developer Community. 2015. GNU GCC Speedup Areas. Retrieved on September 04, 2019 from https:\/\/gcc.gnu.org\/wiki\/Speedup_areas."},{"key":"e_1_2_1_22_1","volume-title":"GNU Compiler Collection Internals. Retrieved on","author":"Richard","year":"2019","unstructured":"Richard M. Stallman and the GCC Developer Community. 2018 . GNU Compiler Collection Internals. Retrieved on September 04, 2019 from https:\/\/gcc.gnu.org\/onlinedocs\/gccint.pdf. Richard M. Stallman and the GCC Developer Community. 2018. GNU Compiler Collection Internals. Retrieved on September 04, 2019 from https:\/\/gcc.gnu.org\/onlinedocs\/gccint.pdf."},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201910)","author":"Villarreal J.","year":"2010","unstructured":"J. Villarreal , A. Park , W. Najjar , and R. Halstead . 2010. Designing modular hardware accelerators in C with ROCCC 2.0 . In Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201910) . 127--134. DOI:https:\/\/doi.org\/10.1109\/FCCM. 2010 .28 10.1109\/FCCM.2010.28 J. Villarreal, A. Park, W. Najjar, and R. Halstead. 2010. Designing modular hardware accelerators in C with ROCCC 2.0. In Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201910). 127--134. DOI:https:\/\/doi.org\/10.1109\/FCCM.2010.28"},{"key":"e_1_2_1_25_1","volume-title":"Retrieved on","year":"2017","unstructured":"Xilinx. 2017 . Vivado Design Suite . Retrieved on September 04, 2019 from http:\/\/www.xilinx.com. Xilinx. 2017. Vivado Design Suite. Retrieved on September 04, 2019 from http:\/\/www.xilinx.com."}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3356475","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3356475","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:22:54Z","timestamp":1750202574000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3356475"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10,31]]},"references-count":24,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2019,12,31]]}},"alternative-id":["10.1145\/3356475"],"URL":"https:\/\/doi.org\/10.1145\/3356475","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,10,31]]},"assertion":[{"value":"2017-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-10-31","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}