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Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2019,11,30]]},"abstract":"<jats:p>Monolithic-3D-integration (M3D) improves the performance and energy efficiency of 3D ICs over conventional through-silicon-vias-based counterparts. The smaller dimensions of monolithic inter-tier vias offer high-density integration, the flexibility of partitioning logic blocks across multiple tiers, and significantly reduced total wire-length enable high-performance and energy-efficiency. However, the performance of M3D ICs degrades due to the presence of electrostatic coupling when the inter-layer-dielectric thickness between two adjacent tiers is less than 50nm. In this work, we evaluate the performance of an M3D-enabled Network-on-chip (NoC) architecture in the presence of electrostatic coupling. Electrostatic coupling induces significant delay and energy overheads for the multi-tier NoC routers. This in turn results in considerable performance degradation if the NoC design methodology does not incorporate the effects of electrostatic coupling. We demonstrate that electrostatic coupling degrades the energy-delay-product of an M3D NoC by 18.1% averaged over eight different applications from SPLASH-2 and PARSEC benchmark suites. As a countermeasure, we advocate the adoption of electrostatic coupling-aware M3D NoC design methodology. Experimental results show that the coupling-aware M3D NoC reduces performance penalty by lowering the number of multi-tier routers significantly.<\/jats:p>","DOI":"10.1145\/3357158","type":"journal-article","created":{"date-parts":[[2019,9,17]],"date-time":"2019-09-17T12:18:07Z","timestamp":1568722687000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on Chip"],"prefix":"10.1145","volume":"24","author":[{"given":"Dongjin","family":"Lee","sequence":"first","affiliation":[{"name":"Washington State University, Pullman, Washington"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sourav","family":"Das","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, Washington"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Janardhan Rao","family":"Doppa","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, Washington"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Partha Pratim","family":"Pande","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, Washington"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[{"name":"Duke University, Duke University, Durham, NC"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,9,17]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the 17th International Symposium on Quality Electronic Design (ISQED\u201916)","author":"Acharya K.","unstructured":"K. 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Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation. In Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201917). 20.3.1--20.3.4.  F. Andrieu R. Berthelon R. Boumchedda G. Tricaud L. Brunet P. Batude B. Mathieu E. Avelar A. Ayres de Sousa G. Cibrario O. Rozeau J. Lacord O. Billoint C. Fenouillet-B\u00e9ranger S. Guissi D. Fried P. Morin J. P. Noel B. Giraud S. Thuries F. Arnaud and M. Vinet. 2017. Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation. 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