{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T23:43:34Z","timestamp":1780357414473,"version":"3.54.1"},"reference-count":35,"publisher":"Association for Computing Machinery (ACM)","issue":"5s","license":[{"start":{"date-parts":[[2019,10,7]],"date-time":"2019-10-07T00:00:00Z","timestamp":1570406400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2721.001"],"award-info":[{"award-number":["2721.001"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2019,10,31]]},"abstract":"<jats:p>Networks-on-chip (NoCs) have become the standard for interconnect solutions in industrial designs ranging from client CPUs to many-core chip-multiprocessors. Since NoCs play a vital role in system performance and power consumption, pre-silicon evaluation environments include cycle-accurate NoC simulators. Long simulations increase the execution time of evaluation frameworks, which are already notoriously slow, and prohibit design-space exploration. Existing analytical NoC models, which assume fair arbitration, cannot replace these simulations since industrial NoCs typically employ priority schedulers and multiple priority classes. To address this limitation, we propose a systematic approach to construct priority-aware analytical performance models using micro-architecture specifications and input traffic. Our approach decomposes the given NoC into individual queues with modified service time to enable accurate and scalable latency computations. Specifically, we introduce novel transformations along with an algorithm that iteratively applies these transformations to decompose the queuing system. Experimental evaluations using real architectures and applications show high accuracy of 97% and up to 2.5\u00d7 speedup in full-system simulation.<\/jats:p>","DOI":"10.1145\/3358176","type":"journal-article","created":{"date-parts":[[2019,10,10]],"date-time":"2019-10-10T13:13:05Z","timestamp":1570713185000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":22,"title":["Analytical Performance Models for NoCs with Multiple Priority Traffic Classes"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9294-1603","authenticated-orcid":false,"given":"Sumit K.","family":"Mandal","sequence":"first","affiliation":[{"name":"Arizona State University, Tempe, AZ"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Raid","family":"Ayoub","sequence":"additional","affiliation":[{"name":"Intel Corporation, Hillsboro, OR"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Michael","family":"Kishinevsky","sequence":"additional","affiliation":[{"name":"Intel Corporation, Hillsboro, OR"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Umit Y.","family":"Ogras","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,10,7]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"symp. on Performance Analysis of Systems and Software. 33--42","author":"Agarwal N.","unstructured":"N. Agarwal : A detailed on-chip network model inside a full-system simulator. In 2009 IEEE intl . symp. on Performance Analysis of Systems and Software. 33--42 . N. Agarwal et al. &lsqb;n.d.&rsqb;. GARNET: A detailed on-chip network model inside a full-system simulator. In 2009 IEEE intl. symp. on Performance Analysis of Systems and Software. 33--42."},{"key":"e_1_2_1_2_1","volume-title":"Parallel and Distributed Systems. Proc. 11th Intl Conf. on","volume":"2","author":"Awan I.","unstructured":"I. Awan and R. Fretwell . 2005. Analysis of discrete-time queues with space and service priorities for arbitrary arrival processes . In Parallel and Distributed Systems. Proc. 11th Intl Conf. on , Vol. 2 . 115--119. I. Awan and R. Fretwell. 2005. Analysis of discrete-time queues with space and service priorities for arbitrary arrival processes. In Parallel and Distributed Systems. Proc. 11th Intl Conf. on, Vol. 2. 115--119."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785553"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0166-5316(99)00075-9"},{"key":"e_1_2_1_5_1","unstructured":"D. P. Bertsekas R. G. Gallager and P. Humblet. 1992. Data Networks. Vol. 2. Prentice-Hall International New Jersey.  D. P. Bertsekas R. G. Gallager and P. Humblet. 1992. Data Networks. Vol. 2. Prentice-Hall International New Jersey."},{"key":"e_1_2_1_6_1","volume-title":"Proc. of the Intl. Conf. on Parallel Arch. and Compilation Tech. 72--81","author":"Bienia C.","unstructured":"C. Bienia , S. Kumar , J. P. Singh , and K. Li . 2008. The PARSEC benchmark suite: Characterization and architectural implications . In Proc. of the Intl. Conf. on Parallel Arch. and Compilation Tech. 72--81 . C. Bienia, S. Kumar, J. P. Singh, and K. Li. 2008. The PARSEC benchmark suite: Characterization and architectural implications. In Proc. of the Intl. Conf. on Parallel Arch. and Compilation Tech. 72--81."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2111270"},{"key":"e_1_2_1_9_1","doi-asserted-by":"crossref","unstructured":"G. Bolch S. Greiner H. De Meer and K. S. Trivedi. 2006. Queueing Networks and Markov Chains: Modeling and Performance Evaluation with Computer Science Applications. John Wiley 8 Sons.  G. Bolch S. Greiner H. De Meer and K. S. Trivedi. 2006. Queueing Networks and Markov Chains: Modeling and Performance Evaluation with Computer Science Applications. John Wiley 8 Sons.","DOI":"10.1002\/0471791571"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2777863"},{"key":"e_1_2_1_11_1","volume-title":"Linux Kongress","volume":"18","author":"de Melo A. C.","year":"2010","unstructured":"A. C. de Melo . 2010 . The new linux perf tools . In Linux Kongress , Vol. 18 . A. C. de Melo. 2010. The new linux perf tools. In Linux Kongress, Vol. 18."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.38"},{"key":"e_1_2_1_13_1","volume-title":"Proc. 11th Int. Teletraffic Congr.","author":"Ikehara S.","unstructured":"S. Ikehara and M. Miyazaki . [n.d.]. Approximate analysis of queueing networks with nonpreemptive priority scheduling . In Proc. 11th Int. Teletraffic Congr. S. Ikehara and M. Miyazaki. [n.d.]. Approximate analysis of queueing networks with nonpreemptive priority scheduling. In Proc. 11th Int. Teletraffic Congr."},{"key":"e_1_2_1_14_1","doi-asserted-by":"crossref","unstructured":"J. Jeffers J. Reinders and A. Sodani. 2016. Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition. Morgan Kaufmann.  J. Jeffers J. Reinders and A. Sodani. 2016. Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition. Morgan Kaufmann.","DOI":"10.1016\/B978-0-12-809194-4.00002-8"},{"key":"e_1_2_1_15_1","volume-title":"2013 IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS). 86--96","author":"Jiang N.","unstructured":"N. Jiang A detailed and flexible cycle-accurate network-on-chip simulator . In 2013 IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS). 86--96 . N. Jiang et al. [n.d.]. A detailed and flexible cycle-accurate network-on-chip simulator. In 2013 IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS). 86--96."},{"key":"e_1_2_1_16_1","article-title":"Modelling and analysis of priority queueing systems with multi-class self-similar network traffic: A novel and efficient queue-decomposition approach","volume":"57","author":"Jin X.","year":"2009","unstructured":"X. Jin and G. Min . 2009 . Modelling and analysis of priority queueing systems with multi-class self-similar network traffic: A novel and efficient queue-decomposition approach . IEEE Trans. on Communications 57 , 5 (2009). X. Jin and G. Min. 2009. Modelling and analysis of priority queueing systems with multi-class self-similar network traffic: A novel and efficient queue-decomposition approach. IEEE Trans. on Communications 57, 5 (2009).","journal-title":"IEEE Trans. on Communications"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/1148882.1148891"},{"key":"e_1_2_1_18_1","volume-title":"Asia and South Pacific Design Autom. Conf. 113--118","author":"Kashif H.","unstructured":"H. Kashif and H. Patel . 2014. Bounding buffer space requirements for real-time priority-aware networks . In Asia and South Pacific Design Autom. Conf. 113--118 . H. Kashif and H. Patel. 2014. Bounding buffer space requirements for real-time priority-aware networks. In Asia and South Pacific Design Autom. Conf. 113--118."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196116"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2178620"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763121"},{"key":"e_1_2_1_22_1","doi-asserted-by":"crossref","unstructured":"P. S. Magnusson etal [n.d.]. Simics: A full system simulation platform. Computer 35 2 ([n.\u00a0d.]) 50--58.  P. S. Magnusson et al. [n.d.]. Simics: A full system simulation platform. Computer 35 2 ([n.\u00a0d.]) 50--58.","DOI":"10.1109\/2.982916"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2061613"},{"key":"e_1_2_1_24_1","volume-title":"Proc. of Intl. Workshop on System Level Interconnect Prediction. 24--31","author":"Ogras U. Y.","unstructured":"U. Y. Ogras , Y. Emre , J. Xu , T. Kam , and M. Kishinevsky . 2012. Energy-guided exploration of on-chip network design for exa-scale computing . In Proc. of Intl. Workshop on System Level Interconnect Prediction. 24--31 . U. Y. Ogras, Y. Emre, J. Xu, T. Kam, and M. Kishinevsky. 2012. Energy-guided exploration of on-chip network design for exa-scale computing. In Proc. of Intl. Workshop on System Level Interconnect Prediction. 24--31."},{"key":"e_1_2_1_25_1","volume-title":"[n.d.]. xPLORE: Communication Fabric Design and Optimization Framework. Developed at Strategic CAD Labs","author":"Ogras U. Y.","unstructured":"U. Y. Ogras , M. Kishinevsky , and S. Chatterjee . [n.d.]. xPLORE: Communication Fabric Design and Optimization Framework. Developed at Strategic CAD Labs , Intel Corp . U. Y. Ogras, M. Kishinevsky, and S. Chatterjee. [n.d.]. xPLORE: Communication Fabric Design and Optimization Framework. Developed at Strategic CAD Labs, Intel Corp."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.134"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"e_1_2_1_28_1","volume-title":"2009 3rd ACM\/IEEE Interl. Symp. on Networks-on-Chip. 44--53","author":"Qian Y.","unstructured":"Y. Qian , Z. Lu , and W. Dou . [n.d.]. Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip . In 2009 3rd ACM\/IEEE Interl. Symp. on Networks-on-Chip. 44--53 . Y. Qian, Z. Lu, and W. Dou. [n.d.]. Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip. In 2009 3rd ACM\/IEEE Interl. Symp. on Networks-on-Chip. 44--53."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2474393"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/3075564.3095086"},{"key":"e_1_2_1_31_1","unstructured":"E. Rotem and S. P. Engineer. 2015. Intel architecture code name skylake deep dive: A new architecture to manage power performance and energy efficiency. In Intel Developer Forum.  E. Rotem and S. P. Engineer. 2015. Intel architecture code name skylake deep dive: A new architecture to manage power performance and energy efficiency. In Intel Developer Forum."},{"key":"e_1_2_1_32_1","doi-asserted-by":"crossref","unstructured":"M. P. Singh and M. K. Jain. 2014. Evolution of processor architecture in mobile phones. Intl. Journ. of Computer Applications 90 4 (2014).  M. P. Singh and M. K. Jain. 2014. Evolution of processor architecture in mobile phones. Intl. Journ. of Computer Applications 90 4 (2014).","DOI":"10.5120\/15564-4339"},{"key":"e_1_2_1_34_1","volume-title":"Proc. of the conf. on DATE. 272","author":"Wettin P.","year":"2014","unstructured":"P. Wettin 2014 . Performance evaluation of wireless NoCs in presence of irregular network routing strategies . In Proc. of the conf. on DATE. 272 . P. Wettin et al. 2014. Performance evaluation of wireless NoCs in presence of irregular network routing strategies. In Proc. of the conf. on DATE. 272."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-009-0265-x"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2017.2686856"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3358176","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3358176","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:32:58Z","timestamp":1750199578000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3358176"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10,7]]},"references-count":35,"journal-issue":{"issue":"5s","published-print":{"date-parts":[[2019,10,31]]}},"alternative-id":["10.1145\/3358176"],"URL":"https:\/\/doi.org\/10.1145\/3358176","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,10,7]]},"assertion":[{"value":"2019-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-10-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}