{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T17:50:37Z","timestamp":1760205037953,"version":"3.41.0"},"reference-count":71,"publisher":"Association for Computing Machinery (ACM)","issue":"5s","license":[{"start":{"date-parts":[[2019,10,7]],"date-time":"2019-10-07T00:00:00Z","timestamp":1570406400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2019,10,31]]},"abstract":"<jats:p>\n            Phase-change memory (PCM) devices have multiple banks to serve memory requests\n            <jats:italic>in parallel<\/jats:italic>\n            . Unfortunately, if two requests go to the\n            <jats:italic>same bank<\/jats:italic>\n            , they have to be served\n            <jats:italic>one after another<\/jats:italic>\n            , leading to lower\n            <jats:italic>system performance<\/jats:italic>\n            . We observe that a modern PCM bank is implemented as a collection of\n            <jats:italic>partitions<\/jats:italic>\n            that operate mostly\n            <jats:italic>independently<\/jats:italic>\n            while\n            <jats:italic>sharing<\/jats:italic>\n            a\n            <jats:italic>few<\/jats:italic>\n            global peripheral structures, which include the sense amplifiers (to read) and the write drivers (to write). Based on this observation, we propose\n            <jats:bold>PALP<\/jats:bold>\n            , a\n            <jats:italic>new<\/jats:italic>\n            mechanism that\n            <jats:italic>enables<\/jats:italic>\n            partition-level parallelism within each PCM bank, and\n            <jats:italic>exploits<\/jats:italic>\n            such parallelism by using the memory controller\u2019s access scheduling decisions. PALP consists of\n            <jats:italic>three<\/jats:italic>\n            new contributions.\n            <jats:bold>First<\/jats:bold>\n            , we introduce\n            <jats:italic>new<\/jats:italic>\n            PCM commands to enable parallelism in a bank\u2019s partitions in order to resolve the\n            <jats:bold>read-write<\/jats:bold>\n            bank conflicts, with\n            <jats:italic>no<\/jats:italic>\n            changes needed to PCM logic or its interface.\n            <jats:bold>Second<\/jats:bold>\n            , we propose\n            <jats:italic>simple<\/jats:italic>\n            circuit modifications that introduce a new operating mode for the write drivers, in addition to their\n            <jats:italic>default<\/jats:italic>\n            mode of serving write requests. When configured in this new mode, the write drivers can resolve the\n            <jats:bold>read-read<\/jats:bold>\n            bank conflicts, working\n            <jats:italic>jointly<\/jats:italic>\n            with the sense amplifiers.\n            <jats:bold>Finally<\/jats:bold>\n            , we propose a\n            <jats:italic>new<\/jats:italic>\n            access scheduling mechanism in PCM that improves performance by prioritizing those requests that exploit partition-level parallelism over other requests, including the long outstanding ones. While doing so, the memory controller also guarantees starvation-freedom and the PCM\u2019s running-average-power-limit (RAPL).\n          <\/jats:p>\n          <jats:p>We evaluate PALP with workloads from the MiBench and SPEC CPU2017 Benchmark suites. Our results show that PALP reduces average PCM access latency by 23%, and improves average system performance by 28% compared to the state-of-the-art approaches.<\/jats:p>","DOI":"10.1145\/3358180","type":"journal-article","created":{"date-parts":[[2019,10,10]],"date-time":"2019-10-10T13:13:05Z","timestamp":1570713185000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":23,"title":["Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories"],"prefix":"10.1145","volume":"18","author":[{"given":"Shihao","family":"Song","sequence":"first","affiliation":[{"name":"Drexel University, Philadelphia, Pennsylvania"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5673-2636","authenticated-orcid":false,"given":"Anup","family":"Das","sequence":"additional","affiliation":[{"name":"Drexel University, Philadelphia, Pennsylvania"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich, Z\u00fcrich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nagarajan","family":"Kandasamy","sequence":"additional","affiliation":[{"name":"Drexel University, Philadelphia, Pennsylvania"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,10,7]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"crossref","unstructured":"Shoaib Akram Jennifer B. Sartor Kathryn S. McKinley and Lieven Eeckhout. 2018. Write-rationing garbage collection for hybrid memories. In Programming Language Design and Implementation (PLDI).  Shoaib Akram Jennifer B. Sartor Kathryn S. McKinley and Lieven Eeckhout. 2018. Write-rationing garbage collection for hybrid memories. In Programming Language Design and Implementation (PLDI).","DOI":"10.1145\/3192366.3192392"},{"volume-title":"International Symposium on Computer Architecture (ISCA).","author":"Arjomand Mohammad","key":"e_1_2_1_2_1","unstructured":"Mohammad Arjomand , Mahmut T. Kandemir , Anand Sivasubramaniam , and Chita R. Das . 2016. Boosting access parallelism to PCM-based main memory . In International Symposium on Computer Architecture (ISCA). Mohammad Arjomand, Mahmut T. Kandemir, Anand Sivasubramaniam, and Chita R. Das. 2016. Boosting access parallelism to PCM-based main memory. In International Symposium on Computer Architecture (ISCA)."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/3290384"},{"key":"e_1_2_1_4_1","unstructured":"JEDEC Solid State Technology Association et al. 2012. JEDEC standard: DDR4 SDRAM. JESD79-4 Sep (2012).  JEDEC Solid State Technology Association et al. 2012. JEDEC standard: DDR4 SDRAM. JESD79-4 Sep (2012)."},{"key":"e_1_2_1_5_1","first-page":"667","article-title":"Apparatus and methods to perform read-while write (RWW) operations","volume":"15","author":"Barkley Gerald John","year":"2017","unstructured":"Gerald John Barkley , Daniele Vimercati , and Pierguido Garofalo . 2017 . Apparatus and methods to perform read-while write (RWW) operations . US Patent App. 15\/688 , 667 . Gerald John Barkley, Daniele Vimercati, and Pierguido Garofalo. 2017. Apparatus and methods to perform read-while write (RWW) operations. US Patent App. 15\/688,667.","journal-title":"US Patent App."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_7_1","volume-title":"International Conference on Computer Design (ICCD).","author":"Bock Santiago","year":"2016","unstructured":"Santiago Bock , Bruce R. Childers , Rami Melhem , and Daniel Moss\u00e9 . 2016 . Concurrent migration of multiple optoptpages in software-managed hybrid main memory . In International Conference on Computer Design (ICCD). Santiago Bock, Bruce R. Childers, Rami Melhem, and Daniel Moss\u00e9. 2016. Concurrent migration of multiple optoptpages in software-managed hybrid main memory. In International Conference on Computer Design (ICCD)."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/3185768.3185771"},{"volume-title":"International Memory Workshop (IMW).","author":"Castellani N.","key":"e_1_2_1_9_1","unstructured":"N. Castellani , G. Navarro , V. Sousa , P. Zuliani , R. Annunziata , M. Borghi , L. Perniola , and G. Reimbold . 2016. Comparative analysis of program\/read disturb robustness for GeSbTe-based phase-change memory devices . In International Memory Workshop (IMW). N. Castellani, G. Navarro, V. Sousa, P. Zuliani, R. Annunziata, M. Borghi, L. Perniola, and G. Reimbold. 2016. Comparative analysis of program\/read disturb robustness for GeSbTe-based phase-change memory devices. In International Memory Workshop (IMW)."},{"key":"e_1_2_1_10_1","volume-title":"DRAMPower: Open-source DRAM power 8 energy estimation tool. URL: http:\/\/www.drampower.info","author":"Chandrasekar Karthik","year":"2012","unstructured":"Karthik Chandrasekar , Christian Weis , Yonghui Li , Benny Akesson , Norbert Wehn , and Kees Goossens . 2012. DRAMPower: Open-source DRAM power 8 energy estimation tool. URL: http:\/\/www.drampower.info ( 2012 ). Karthik Chandrasekar, Christian Weis, Yonghui Li, Benny Akesson, Norbert Wehn, and Kees Goossens. 2012. DRAMPower: Open-source DRAM power 8 energy estimation tool. URL: http:\/\/www.drampower.info (2012)."},{"key":"e_1_2_1_11_1","first-page":"885","article-title":"Programming method of controlling the amount of write current applied to phase change memory device and write driver circuit therefor","volume":"6","author":"Cho Baek-Hyung","year":"2005","unstructured":"Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , and Byung-Gil Choi . 2005 . Programming method of controlling the amount of write current applied to phase change memory device and write driver circuit therefor . US Patent 6 , 885 ,602. Baek-Hyung Cho, Woo-Yeong Cho, Hyung-Rok Oh, and Byung-Gil Choi. 2005. Programming method of controlling the amount of write current applied to phase change memory device and write driver circuit therefor. US Patent 6,885,602.","journal-title":"US Patent"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"e_1_2_1_13_1","volume-title":"International Symposium on Low Power Electronics and Design (ISLPED).","author":"David Howard","year":"2010","unstructured":"Howard David , Eugene Gorbatov , Ulf R Hanebutte , Rahul Khanna , and Christian Le . 2010 . RAPL: Memory power estimation and capping . In International Symposium on Low Power Electronics and Design (ISLPED). Howard David, Eugene Gorbatov, Ulf R Hanebutte, Rahul Khanna, and Christian Le. 2010. RAPL: Memory power estimation and capping. In International Symposium on Low Power Electronics and Design (ISLPED)."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630086"},{"key":"e_1_2_1_15_1","first-page":"875","article-title":"High voltage tolerant word-line driver","volume":"9","author":"Dray Cyrille","year":"2018","unstructured":"Cyrille Dray and Liqiong Wei . 2018 . High voltage tolerant word-line driver . US Patent 9 , 875 ,783. Cyrille Dray and Liqiong Wei. 2018. High voltage tolerant word-line driver. US Patent 9,875,783.","journal-title":"US Patent"},{"key":"e_1_2_1_16_1","volume-title":"SPICE: The Theory and Practice of Software Process Improvement and Capability Determination.","author":"Emam Khaled El","year":"1997","unstructured":"Khaled El Emam , Walcelio Melo , and Jean-Normand Drouin . 1997 . SPICE: The Theory and Practice of Software Process Improvement and Capability Determination. Khaled El Emam, Walcelio Melo, and Jean-Normand Drouin. 1997. SPICE: The Theory and Practice of Software Process Improvement and Capability Determination."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2018.8388839"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/3309697.3331482"},{"key":"e_1_2_1_19_1","first-page":"048","article-title":"Programming memory devices","volume":"15","author":"Goda Akira","year":"2018","unstructured":"Akira Goda , Tommaso Vali , Carmine Miccoli , and Pranav Kalavade . 2018 . Programming memory devices . US Patent App. 15\/477 , 048 . Akira Goda, Tommaso Vali, Carmine Miccoli, and Pranav Kalavade. 2018. Programming memory devices. US Patent App. 15\/477,048.","journal-title":"US Patent App."},{"volume-title":"Workshop on Workload Characterization (WWC).","author":"Guthaus Matthew R.","key":"e_1_2_1_20_1","unstructured":"Matthew R. Guthaus , Jeffrey S. Ringenberg , Dan Ernst , Todd M. Austin , Trevor Mudge , and Richard B. Brown . 2001. MiBench: A free, commercially representative embedded benchmark suite . In Workshop on Workload Characterization (WWC). Matthew R. Guthaus, Jeffrey S. Ringenberg, Dan Ernst, Todd M. Austin, Trevor Mudge, and Richard B. Brown. 2001. MiBench: A free, commercially representative embedded benchmark suite. In Workshop on Workload Characterization (WWC)."},{"key":"e_1_2_1_21_1","volume-title":"Lee","author":"Ham Tae Jun","year":"2013","unstructured":"Tae Jun Ham , Bharath K. Chelepalli , Neng Xue , and Benjamin C . Lee . 2013 . Disintegrated control for energy-efficient and heterogeneous memory systems. In High Performance Computer Architecture (HPCA) . Tae Jun Ham, Bharath K. Chelepalli, Neng Xue, and Benjamin C. Lee. 2013. Disintegrated control for energy-efficient and heterogeneous memory systems. In High Performance Computer Architecture (HPCA)."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322231"},{"key":"e_1_2_1_23_1","doi-asserted-by":"crossref","unstructured":"Hasan Hassan Gennady Pekhimenko Nandita Vijaykumar Vivek Seshadri Donghyuk Lee Oguz Ergin and Onur Mutlu. 2016. ChargeCache: Reducing DRAM latency by exploiting row access locality. In High Performance Computer Architecture (HPCA).  Hasan Hassan Gennady Pekhimenko Nandita Vijaykumar Vivek Seshadri Donghyuk Lee Oguz Ergin and Onur Mutlu. 2016. ChargeCache: Reducing DRAM latency by exploiting row access locality. In High Performance Computer Architecture (HPCA).","DOI":"10.1109\/HPCA.2016.7446096"},{"key":"e_1_2_1_24_1","article-title":"Write activity reduction on non-volatile main memories for embedded chip multiprocessors","volume":"12","author":"Hu Jingtong","year":"2013","unstructured":"Jingtong Hu , Chun Jason Xue , Qingfeng Zhuge , Wei-Che Tseng , and Edwin H.-M. Sha . 2013 . Write activity reduction on non-volatile main memories for embedded chip multiprocessors . ACM Transactions on Embedded Computing 12 , 3 (2013). Jingtong Hu, Chun Jason Xue, Qingfeng Zhuge, Wei-Che Tseng, and Edwin H.-M. Sha. 2013. Write activity reduction on non-volatile main memories for embedded chip multiprocessors. ACM Transactions on Embedded Computing 12, 3 (2013).","journal-title":"ACM Transactions on Embedded Computing"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/1950815.1950854"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.10"},{"key":"e_1_2_1_27_1","volume-title":"ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. In High Performance Computer Architecture (HPCA).","author":"Kim Yoongu","year":"2010","unstructured":"Yoongu Kim , Dongsu Han , Onur Mutlu , and Mor Harchol-Balter . 2010 . ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. In High Performance Computer Architecture (HPCA). Yoongu Kim, Dongsu Han, Onur Mutlu, and Mor Harchol-Balter. 2010. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. In High Performance Computer Architecture (HPCA)."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237032"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_2_1_31_1","volume-title":"Phase change memory architecture and the quest for scalability. Commun. ACM 53, 7","author":"Lee Benjamin C.","year":"2010","unstructured":"Benjamin C. Lee , Engin Ipek , Onur Mutlu , and Doug Burger . 2010. Phase change memory architecture and the quest for scalability. Commun. ACM 53, 7 ( 2010 ). Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger. 2010. Phase change memory architecture and the quest for scalability. Commun. ACM 53, 7 (2010)."},{"key":"e_1_2_1_32_1","doi-asserted-by":"crossref","unstructured":"B. C. Lee P. Zhou J. Yang Y. Zhang B. Zhao E. Ipek O. Mutlu and D. Burger. 2010. Phase-change technology and the future of main memory. IEEE Micro 30 1 (2010).  B. C. Lee P. Zhou J. Yang Y. Zhang B. Zhao E. Ipek O. Mutlu and D. Burger. 2010. Phase-change technology and the future of main memory. IEEE Micro 30 1 (2010).","DOI":"10.1109\/MM.2010.24"},{"key":"e_1_2_1_33_1","volume-title":"Patt","author":"Lee Chang Joo","year":"2010","unstructured":"Chang Joo Lee , Veynu Narasiman , Eiman Ebrahimi , Onur Mutlu , and Yale N . Patt . 2010 . DRAM-aware last-level cache writeback: Reducing write-caused interference in memory systems. (2010). Chang Joo Lee, Veynu Narasiman, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt. 2010. DRAM-aware last-level cache writeback: Reducing write-caused interference in memory systems. (2010)."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/CLUSTER.2017.130"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/2979143"},{"key":"e_1_2_1_36_1","unstructured":"Sihang Liu Aasheesh Kolli Jinglei Ren and Samira Khan. 2018. Crash consistency in encrypted non-volatile main memory systems. In High Performance Computer Architecture (HPCA).  Sihang Liu Aasheesh Kolli Jinglei Ren and Samira Khan. 2018. Crash consistency in encrypted non-volatile main memory systems. In High Performance Computer Architecture (HPCA)."},{"key":"e_1_2_1_37_1","volume-title":"International Memory Workshop (IMW).","author":"Lung Hsiang-Lan","year":"2016","unstructured":"Hsiang-Lan Lung , Christopher P. Miller , Chia-Jung Chen , Scott C. Lewis , Jack Morrish , Tony Perri , Richard C. Jordan , Hsin-Yi Ho , Tu-Shun Chen , Wei-Chih Chien , 2016 . A double-data-rate 2 (DDR2) interface phase-change memory with 533MB\/s read-write data rate and 37.5 ns access latency for memory-type storage class memory applications . In International Memory Workshop (IMW). Hsiang-Lan Lung, Christopher P. Miller, Chia-Jung Chen, Scott C. Lewis, Jack Morrish, Tony Perri, Richard C. Jordan, Hsin-Yi Ho, Tu-Shun Chen, Wei-Chih Chien, et al. 2016. A double-data-rate 2 (DDR2) interface phase-change memory with 533MB\/s read-write data rate and 37.5 ns access latency for memory-type storage class memory applications. In International Memory Workshop (IMW)."},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2012.2"},{"key":"e_1_2_1_39_1","volume-title":"Proceedings of the Workshop on Energy-Efficient Design (WEED).","author":"Meza Justin","year":"2013","unstructured":"Justin Meza , Yixin Luo , Samira Khan , Jishen Zhao , Yuan Xie , and Onur Mutlu . 2013 . A case for efficient hardware\/software cooperative management of storage and memory . In Proceedings of the Workshop on Energy-Efficient Design (WEED). Justin Meza, Yixin Luo, Samira Khan, Jishen Zhao, Yuan Xie, and Onur Mutlu. 2013. A case for efficient hardware\/software cooperative management of storage and memory. In Proceedings of the Workshop on Energy-Efficient Design (WEED)."},{"key":"e_1_2_1_40_1","volume-title":"4Gb: x4, x8, x16 DDR4 SDRAM features, white paper. Micron Technology","author":"Micron D. D. R","year":"2014","unstructured":"D. D. R Micron . 2014. SDRAM , 4Gb: x4, x8, x16 DDR4 SDRAM features, white paper. Micron Technology , Inc ( 2014 ). D. D. R Micron. 2014. SDRAM, 4Gb: x4, x8, x16 DDR4 SDRAM features, white paper. Micron Technology, Inc (2014)."},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2018.8388845"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418973"},{"key":"e_1_2_1_43_1","volume-title":"Reversible electrical switching phenomena in disordered structures. Physical Review Letters","author":"Ovshinsky S.","year":"1968","unstructured":"S. Ovshinsky . 1968. Reversible electrical switching phenomena in disordered structures. Physical Review Letters ( 1968 ). S. Ovshinsky. 1968. Reversible electrical switching phenomena in disordered structures. Physical Review Letters (1968)."},{"key":"e_1_2_1_44_1","volume-title":"John","author":"Panda Reena","year":"2018","unstructured":"Reena Panda , Shuang Song , Joseph Dean , and Lizy K . John . 2018 . Wait of a decade: Did SPEC CPU 2017 broaden the performance horizon?. In High Performance Computer Architecture (HPCA) . Reena Panda, Shuang Song, Joseph Dean, and Lizy K. John. 2018. Wait of a decade: Did SPEC CPU 2017 broaden the performance horizon?. In High Performance Computer Architecture (HPCA)."},{"key":"e_1_2_1_45_1","volume-title":"Zhichun Zhu, and Gokhan Memik.","author":"Pourshirazi Bahareh","year":"2018","unstructured":"Bahareh Pourshirazi , Majed Valad Beigi , Zhichun Zhu, and Gokhan Memik. 2018 . WALL : A writeback-aware LLC management for PCM-based main memory systems. In Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE) . Bahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu, and Gokhan Memik. 2018. WALL: A writeback-aware LLC management for PCM-based main memory systems. In Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE)."},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/3292009"},{"volume-title":"International Symposium on Computer Architecture (ISCA).","author":"Qureshi Moinuddin K.","key":"e_1_2_1_47_1","unstructured":"Moinuddin K. Qureshi , Michele M. Franceschini , Ashish Jagmohan , and Luis A. Lastras . 2012. PreSET: Improving performance of phase change memories by exploiting asymmetry in write times . In International Symposium on Computer Architecture (ISCA). Moinuddin K. Qureshi, Michele M. Franceschini, Ashish Jagmohan, and Luis A. Lastras. 2012. PreSET: Improving performance of phase change memories by exploiting asymmetry in write times. In International Symposium on Computer Architecture (ISCA)."},{"volume-title":"International Symposium on Computer Architecture (ISCA).","author":"Qureshi Moinuddin K.","key":"e_1_2_1_48_1","unstructured":"Moinuddin K. Qureshi , Michele M. Franceschini , Luis A. Lastras-Monta\u00f1o , and John P. Karidis . 2010. Morphable memory system: A robust architecture for exploiting multi-level phase change memories . In International Symposium on Computer Architecture (ISCA). Moinuddin K. Qureshi, Michele M. Franceschini, Luis A. Lastras-Monta\u00f1o, and John P. Karidis. 2010. Morphable memory system: A robust architecture for exploiting multi-level phase change memories. In International Symposium on Computer Architecture (ISCA)."},{"key":"e_1_2_1_49_1","volume-title":"Lastras-Montano","author":"Qureshi Moinuddin K.","year":"2010","unstructured":"Moinuddin K. Qureshi , Michele M. Franceschini , and Luis A . Lastras-Montano . 2010 . Improving read performance of phase change memories via write cancellation and write pausing. In High Performance Computer Architecture (HPCA) . Moinuddin K. Qureshi, Michele M. Franceschini, and Luis A. Lastras-Montano. 2010. Improving read performance of phase change memories via write cancellation and write pausing. In High Performance Computer Architecture (HPCA)."},{"volume-title":"International Symposium on Computer Architecture (ISCA).","author":"Qureshi Moinuddin K.","key":"e_1_2_1_50_1","unstructured":"Moinuddin K. Qureshi , Vijayalakshmi Srinivasan , and Jude A. Rivers . 2009. Scalable high performance main memory system using phase-change memory technology . In International Symposium on Computer Architecture (ISCA). Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, and Jude A. Rivers. 2009. Scalable high performance main memory system using phase-change memory technology. In International Symposium on Computer Architecture (ISCA)."},{"volume-title":"International Symposium on Computer Architecture (ISCA).","author":"Rixner Scott","key":"e_1_2_1_51_1","unstructured":"Scott Rixner , William J. Dally , Ujval J. Kapasi , Peter Mattson , and John D. Owens . 2000. Memory access scheduling . In International Symposium on Computer Architecture (ISCA). Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter Mattson, and John D. Owens. 2000. Memory access scheduling. In International Symposium on Computer Architecture (ISCA)."},{"key":"e_1_2_1_52_1","first-page":"848","article-title":"Memory write driver, method and system","volume":"15","author":"Sandhu Bal S.","year":"2018","unstructured":"Bal S. Sandhu , Cezary Pietrzyk , and George McNeil Lattimore . 2018 . Memory write driver, method and system . US Patent App. 15\/904 , 848 . Bal S. Sandhu, Cezary Pietrzyk, and George McNeil Lattimore. 2018. Memory write driver, method and system. US Patent App. 15\/904,848.","journal-title":"US Patent App."},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479101"},{"volume-title":"International Symposium on Computer Architecture (ISCA).","author":"Seong Nak Hee","key":"e_1_2_1_54_1","unstructured":"Nak Hee Seong , Dong Hyuk Woo , and Hsien-Hsin S. Lee . 2010. Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized optaddress mapping . In International Symposium on Computer Architecture (ISCA). Nak Hee Seong, Dong Hyuk Woo, and Hsien-Hsin S. Lee. 2010. Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized optaddress mapping. In International Symposium on Computer Architecture (ISCA)."},{"volume-title":"International Symposium on Computer Architecture (ISCA).","author":"Seshadri Vivek","key":"e_1_2_1_55_1","unstructured":"Vivek Seshadri , Abhishek Bhowmick , Onur Mutlu , Phillip B. Gibbons , Michael A. Kozuch , and Todd C. Mowry . 2014. The dirty-block index . In International Symposium on Computer Architecture (ISCA). Vivek Seshadri, Abhishek Bhowmick, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, and Todd C. Mowry. 2014. The dirty-block index. In International Symposium on Computer Architecture (ISCA)."},{"key":"e_1_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228414"},{"key":"e_1_2_1_57_1","doi-asserted-by":"crossref","unstructured":"Shihao Song Anup Das Onur Mutlu and Nagrajan Kandasamy. 2019. Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories. https:\/\/github.com\/drexel-DISCO\/PALP.  Shihao Song Anup Das Onur Mutlu and Nagrajan Kandasamy. 2019. Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories. https:\/\/github.com\/drexel-DISCO\/PALP.","DOI":"10.1145\/3358180"},{"volume-title":"International Symposium on Computer Architecture (ISCA).","author":"Stuecheli Jeffrey","key":"e_1_2_1_58_1","unstructured":"Jeffrey Stuecheli , Dimitris Kaseridis , David Daly , Hillery C. Hunter , and Lizy K. John . 2010. The virtual write queue: Coordinating DRAM and last-level cache policies . In International Symposium on Computer Architecture (ISCA). Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, and Lizy K. John. 2010. The virtual write queue: Coordinating DRAM and last-level cache policies. In International Symposium on Computer Architecture (ISCA)."},{"key":"e_1_2_1_59_1","doi-asserted-by":"crossref","unstructured":"C. Villa. 2018. PCM array architecture and management. In Phase Change Memory.  C. Villa. 2018. PCM array architecture and management. In Phase Change Memory.","DOI":"10.1007\/978-3-319-69053-7_10"},{"key":"e_1_2_1_60_1","volume-title":"International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).","author":"Villa Corrado","year":"2010","unstructured":"Corrado Villa , Duane Mills , Gerald Barkley , Hari Giduturi , Stefan Schippers , and Daniele Vimercati . 2010 . A 45nm 1Gb 1.8 V phase-change memory . In International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). Corrado Villa, Duane Mills, Gerald Barkley, Hari Giduturi, Stefan Schippers, and Daniele Vimercati. 2010. A 45nm 1Gb 1.8 V phase-change memory. In International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)."},{"key":"e_1_2_1_61_1","article-title":"WADE: Writeback-aware dynamic cache management for NVM-based main memory system","volume":"10","author":"Wang Zhe","year":"2013","unstructured":"Zhe Wang , Shuchang Shan , Ting Cao , Junli Gu , Yi Xu , Shuai Mu , Yuan Xie , and Daniel A. Jim\u00e9nez . 2013 . WADE: Writeback-aware dynamic cache management for NVM-based main memory system . ACM Transactions on Architecture and Code Optimization (TACO) 10 , 4 (2013). Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Shuai Mu, Yuan Xie, and Daniel A. Jim\u00e9nez. 2013. WADE: Writeback-aware dynamic cache management for NVM-based main memory system. ACM Transactions on Architecture and Code Optimization (TACO) 10, 4 (2013).","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"},{"key":"e_1_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/2597652.2597661"},{"key":"e_1_2_1_63_1","doi-asserted-by":"crossref","DOI":"10.1109\/TED.2003.818594","article-title":"Sensitivity of double-gate and FinFETDevices to process variations","volume":"50","author":"Xiong Shiying","year":"2003","unstructured":"Shiying Xiong and Jeffrey Bokor . 2003 . Sensitivity of double-gate and FinFETDevices to process variations . IEEE Transactions on Electron Devices 50 , 11 (2003). Shiying Xiong and Jeffrey Bokor. 2003. Sensitivity of double-gate and FinFETDevices to process variations. IEEE Transactions on Electron Devices 50, 11 (2003).","journal-title":"IEEE Transactions on Electron Devices"},{"key":"e_1_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378661"},{"key":"e_1_2_1_65_1","article-title":"Efficient data mapping and buffering techniques for multilevel cell phase-change memories","volume":"11","author":"Yoon Hanbin","year":"2015","unstructured":"Hanbin Yoon , Justin Meza , Naveen Muralimanohar , Norman P. Jouppi , and Onur Mutlu . 2015 . Efficient data mapping and buffering techniques for multilevel cell phase-change memories . ACM Transactions on Architecture and Code Optimization (TACO) 11 , 4 (2015). Hanbin Yoon, Justin Meza, Naveen Muralimanohar, Norman P. Jouppi, and Onur Mutlu. 2015. Efficient data mapping and buffering techniques for multilevel cell phase-change memories. ACM Transactions on Architecture and Code Optimization (TACO) 11, 4 (2015).","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"},{"key":"e_1_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124555"},{"key":"e_1_2_1_67_1","doi-asserted-by":"crossref","unstructured":"Jianhui Yue and Yifeng Zhu. 2013. Accelerating write by exploiting PCM asymmetries. In High Performance Computer Architecture (HPCA).  Jianhui Yue and Yifeng Zhu. 2013. Accelerating write by exploiting PCM asymmetries. In High Performance Computer Architecture (HPCA).","DOI":"10.1109\/HPCA.2013.6522326"},{"key":"e_1_2_1_68_1","unstructured":"Jianhui Yue and Yifeng Zhu. 2013. Exploiting subarrays inside a bank to improve phase change memory performance. In Design Automation 8 Test in Europe Conference 8 Exhibition (DATE).  Jianhui Yue and Yifeng Zhu. 2013. Exploiting subarrays inside a bank to improve phase change memory performance. In Design Automation 8 Test in Europe Conference 8 Exhibition (DATE)."},{"key":"e_1_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001192"},{"key":"e_1_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.47"},{"key":"e_1_2_1_71_1","volume-title":"International Symposium on Low Power Electronics and Design (ISLPED).","author":"Zhou Wen","year":"2016","unstructured":"Wen Zhou , Dan Feng , Yu Hua , Jingning Liu , Fangting Huang , and Yu Chen . 2016 . An efficient parallel scheduling scheme on multi-partition PCM architecture . In International Symposium on Low Power Electronics and Design (ISLPED). Wen Zhou, Dan Feng, Yu Hua, Jingning Liu, Fangting Huang, and Yu Chen. 2016. An efficient parallel scheduling scheme on multi-partition PCM architecture. In International Symposium on Low Power Electronics and Design (ISLPED)."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3358180","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3358180","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:32:58Z","timestamp":1750199578000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3358180"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10,7]]},"references-count":71,"journal-issue":{"issue":"5s","published-print":{"date-parts":[[2019,10,31]]}},"alternative-id":["10.1145\/3358180"],"URL":"https:\/\/doi.org\/10.1145\/3358180","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2019,10,7]]},"assertion":[{"value":"2019-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-10-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}