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Embed. Comput. Syst."],"published-print":{"date-parts":[[2019,10,31]]},"abstract":"<jats:p>The adoption of High-Level Synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area\/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.<\/jats:p>","DOI":"10.1145\/3358182","type":"journal-article","created":{"date-parts":[[2019,10,10]],"date-time":"2019-10-10T09:13:05Z","timestamp":1570698785000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":20,"title":["High-Level Synthesis of Approximate Designs under Real-Time Constraints"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1959-1755","authenticated-orcid":false,"given":"Marcos T.","family":"Leipnitz","sequence":"first","affiliation":[{"name":"Informatics Institute - Federal University of Rio Grande do Sul, Brazil"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gabriel L.","family":"Nazar","sequence":"additional","affiliation":[{"name":"Informatics Institute - Federal University of Rio Grande do Sul, Brazil"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,10,7]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"2015 IEEE International Symposium on Circuits and Systems (ISCAS). 2884--2887","author":"Aksoy L.","unstructured":"L. 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In Proceedings of the 49th Annual Design Automation Conference (DAC\u201912). ACM, New York, NY, USA, 820--825."},{"key":"e_1_2_1_16_1","volume-title":"FPGAs for Software Programmers","author":"Koch Dirk","unstructured":"Dirk Koch , Frank Hannig , and Daniel Ziener . 2016. FPGAs for Software Programmers ( 1 st ed.). Springer Publishing Company, Inc orporated. Dirk Koch, Frank Hannig, and Daniel Ziener. 2016. FPGAs for Software Programmers (1st ed.). Springer Publishing Company, Incorporated.","edition":"1"},{"key":"e_1_2_1_17_1","volume-title":"Int. Symp. Code Generation and Optimization (CGO). 75--86","author":"Lattner C.","unstructured":"C. Lattner and V. Adve . 2004. LLVM: A compilation framework for lifelong program analysis transformation . In Int. Symp. Code Generation and Optimization (CGO). 75--86 . C. Lattner and V. Adve. 2004. LLVM: A compilation framework for lifelong program analysis transformation. In Int. Symp. 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Nepal , Y. Li , R. I. Bahar , and S. Reda . 2014. ABACUS: A technique for automated behavioral synthesis of approximate computing circuits . In Proc. Conf. Design, Automation 8 Test in Europe (DATE\u201914) . Article 361, 6 pages. K. Nepal, Y. Li, R. I. Bahar, and S. Reda. 2014. ABACUS: A technique for automated behavioral synthesis of approximate computing circuits. In Proc. Conf. Design, Automation 8 Test in Europe (DATE\u201914). Article 361, 6 pages."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629395.1629397"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF00571421"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2281934"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/2654822.2541948"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1993316.1993518"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2906199"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/32.29487"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/2025113.2025133"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2520979"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853213"},{"key":"e_1_2_1_38_1","volume-title":"Retrieved","author":"SIP.","year":"2019","unstructured":"USC- SIP. 2019 . The USC-SIPI Image Database . Retrieved March 29, 2019 from http:\/\/sipi.usc.edu\/database. USC-SIP. 2019. The USC-SIPI Image Database. Retrieved March 29, 2019 from http:\/\/sipi.usc.edu\/database."},{"key":"e_1_2_1_39_1","doi-asserted-by":"crossref","unstructured":"F. Vaverka R. Hrbacek and L. Sekanina. 2016. Evolving component library for approximate high level synthesis. In IEEE Symp. Series on Computational Intelligence (SSCI). 1--8.  F. Vaverka R. Hrbacek and L. Sekanina. 2016. Evolving component library for approximate high level synthesis. In IEEE Symp. Series on Computational Intelligence (SSCI). 1--8.","DOI":"10.1109\/SSCI.2016.7850168"},{"key":"e_1_2_1_40_1","volume-title":"Proc. 52Nd Annu. Design Automation Conference (DAC\u201915)","author":"Venkataramani S.","unstructured":"S. Venkataramani , S. T. Chakradhar , K. Roy , and A. Raghunathan . 2015. Approximate computing and the quest for computing efficiency . In Proc. 52Nd Annu. Design Automation Conference (DAC\u201915) . Article 120, 6 pages. S. Venkataramani, S. T. Chakradhar, K. Roy, and A. Raghunathan. 2015. Approximate computing and the quest for computing efficiency. In Proc. 52Nd Annu. Design Automation Conference (DAC\u201915). Article 120, 6 pages."},{"key":"e_1_2_1_41_1","volume-title":"2014 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED). 27--32","author":"Venkataramani S.","unstructured":"S. Venkataramani , A. Ranjan , K. Roy , and A. Raghunathan . 2014. AxNN: Energy-efficient neuromorphic systems using approximate computing . In 2014 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED). 27--32 . S. Venkataramani, A. Ranjan, K. Roy, and A. Raghunathan. 2014. AxNN: Energy-efficient neuromorphic systems using approximate computing. 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