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The interferences introduce non-determinism and delays in execution time. One of the main interference prone resources are cache memories. In single-core processors, caches comprise multiple private levels. This breaks the isolation principle imposed by avionic standards, such as the ARINC-653. This standard defines partitioned architectures where one partition should never directly interfere with another one. In cache-based architectures, one partition can modify the cache content of another partition. In this paper, we propose a method based on cache locking to reduce the non-determinism and the contention on lower level memories while improving the time performances.<\/jats:p>","DOI":"10.1145\/3358196","type":"journal-article","created":{"date-parts":[[2019,10,10]],"date-time":"2019-10-10T13:13:05Z","timestamp":1570713185000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS"],"prefix":"10.1145","volume":"18","author":[{"given":"Alexy Torres Aurora","family":"Dugo","sequence":"first","affiliation":[{"name":"\u00c9cole Polytechnique de Montr\u00e9al, Montr\u00e9al, QC, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jean-Baptiste","family":"Lefoul","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique de Montr\u00e9al, Montr\u00e9al, QC, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Felipe Gohring","family":"De Magalhaes","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique de Montr\u00e9al, Montr\u00e9al, QC, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dahman","family":"Assal","sequence":"additional","affiliation":[{"name":"Mannarino Systems 8 Software Inc. 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