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The floorplanning problem is solved by means of a novel fine-grained modeling strategy of FPGA resources. Furthermore, differently from other proposals, our approach takes into account several realistic Partial Reconfiguration (PR) floorplanning constraints on FPGAs. FLORA was compared against state-of-the-art floorplanners by means of benchmark suites, showing that it is capable of providing better performance in terms of resource consumption, maximum inter-region, wire-length, and running time required to produce the solutions. Finally, FLORA was utilized to generate placements for a partially-reconfigurable video processing engine that was implemented on a Xilinx Zynq-7020.<\/jats:p>","DOI":"10.1145\/3358202","type":"journal-article","created":{"date-parts":[[2019,10,10]],"date-time":"2019-10-10T13:13:05Z","timestamp":1570713185000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["FLORA"],"prefix":"10.1145","volume":"18","author":[{"given":"Biruk B.","family":"Seyoum","sequence":"first","affiliation":[{"name":"Scuola Superiore Sant\u2019Anna, Pisa, Pisa"}]},{"given":"Alessandro","family":"Biondi","sequence":"additional","affiliation":[{"name":"Scuola Superiore Sant\u2019Anna, Pisa, Pisa"}]},{"given":"Giorgio C.","family":"Buttazzo","sequence":"additional","affiliation":[{"name":"Scuola Superiore Sant\u2019Anna, Pisa, Pisa"}]}],"member":"320","published-online":{"date-parts":[[2019,10,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2079390"},{"key":"e_1_2_1_2_1","volume-title":"https:\/\/s2.smu.edu\/&tilde;manikas\/Benchmarks\/MCNC_Benchmark_Netlists.html. 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PRFloor: An automatic floorplanner for partially reconfigurable FPGA systems. In Proceedings of the 2016 ACM\/SIGDA Int. Symposium on Field-Programmable Gate Arrays (FPGA\u201916)."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2562361"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.61"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.16"},{"key":"e_1_2_1_12_1","volume-title":"IET 1 (08","author":"Singhal Love","year":"2007","unstructured":"Love Singhal and Eli Bozorgzadeh . 2007. SPECIAL SECTION ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS - Multi-layer floorplanning for reconfigurable designs. Computers and Digital Techniques , IET 1 (08 2007 ), 276--294. DOI:https:\/\/doi.org\/10.1049\/iet-cdt:20070012 Love Singhal and Eli Bozorgzadeh. 2007. SPECIAL SECTION ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS - Multi-layer floorplanning for reconfigurable designs. Computers and Digital Techniques, IET 1 (08 2007), 276--294. DOI:https:\/\/doi.org\/10.1049\/iet-cdt:20070012"},{"volume-title":"https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2018_1\/ug909-vivado-partial-reconfiguration.pdf. [Online","year":"2019","key":"e_1_2_1_13_1","unstructured":"ug909-vivado-partial-reconfiguration user guide. 2018. https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2018_1\/ug909-vivado-partial-reconfiguration.pdf. [Online ; accessed 27- March - 2019 ]. ug909-vivado-partial-reconfiguration user guide. 2018. https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2018_1\/ug909-vivado-partial-reconfiguration.pdf. [Online; accessed 27-March-2019]."},{"volume-title":"Proceedings of the 8th Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC\u201912)","author":"Vipin Kizheppatt","key":"e_1_2_1_14_1","unstructured":"Kizheppatt Vipin and Suhaib A. Fahmy . 2012. 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