{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:27:27Z","timestamp":1750220847830,"version":"3.41.0"},"reference-count":41,"publisher":"Association for Computing Machinery (ACM)","issue":"5s","license":[{"start":{"date-parts":[[2019,10,8]],"date-time":"2019-10-08T00:00:00Z","timestamp":1570492800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2019,10,31]]},"abstract":"<jats:p>\n            Recent research on mitigating thermal problems in 3D memories has covered reactive strategies that reduce memory power consumption, and thereby, performance, when the memory temperature reaches the maximum operating limit. Such techniques could benefit from temperature prediction and avoid unnecessary invocations and state transitions of the thermal management strategy. We develop an accurate steady state temperature predictor for thermal management of 3D memories. We utilize the symmetries in the floorplan, along with other design insights, to reduce the predictor\u2019s model parameters, making it lightweight and suitable for runtime thermal management. Using the temperature prediction, we introduce\n            <jats:italic>PredictNcool<\/jats:italic>\n            , a proactive thermal management strategy to reduce application runtime and memory energy. We compare\n            <jats:italic>PredictNcool<\/jats:italic>\n            with two recent thermal management strategies and our experiments show that the proposed optimization results in performance improvements of 28% and 5%, and memory subsystem energy reductions of 38% and 12% (on average).\n          <\/jats:p>","DOI":"10.1145\/3358208","type":"journal-article","created":{"date-parts":[[2019,10,10]],"date-time":"2019-10-10T13:13:05Z","timestamp":1570713185000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["PredictNcool"],"prefix":"10.1145","volume":"18","author":[{"given":"Lokesh","family":"Siddhu","sequence":"first","affiliation":[{"name":"Department of Computer Science and Engineering, Indian Institute of Technology Delhi"}]},{"given":"Preeti Ranjan","family":"Panda","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, Indian Institute of Technology Delhi"}]}],"member":"320","published-online":{"date-parts":[[2019,10,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"crossref","unstructured":"T. Adegbija and A. Gordon-Ross. 2018. TaPT: Temperature-aware dynamic cache optimization for embedded systems. Computers (2018).  T. Adegbija and A. Gordon-Ross. 2018. TaPT: Temperature-aware dynamic cache optimization for embedded systems. Computers (2018).","DOI":"10.3390\/computers7010003"},{"key":"e_1_2_1_2_1","doi-asserted-by":"crossref","unstructured":"R. Ayoub K. R. Indukuri and T. S. Rosing. 2010. Energy efficient proactive thermal management in memory subsystem. In ISLPED.  R. Ayoub K. R. Indukuri and T. S. Rosing. 2010. Energy efficient proactive thermal management in memory subsystem. In ISLPED.","DOI":"10.1145\/1840845.1840884"},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","unstructured":"R. Ayoub and A. Orailoglu. 2010. Performance and energy efficient cache migration approach for thermal management in embedded systems. In GLSVLSI.  R. Ayoub and A. Orailoglu. 2010. Performance and energy efficient cache migration approach for thermal management in embedded systems. In GLSVLSI.","DOI":"10.1145\/1785481.1785565"},{"key":"e_1_2_1_4_1","doi-asserted-by":"crossref","unstructured":"P. Bogdan P. P. Pande H. Amrouch M. Shafique and J. Henkel. 2016. Power and thermal management in massive multicore chips: Theoretical foundation meets architectural innovation and resource allocation. In CASES.  P. Bogdan P. P. Pande H. Amrouch M. Shafique and J. Henkel. 2016. Power and thermal management in massive multicore chips: Theoretical foundation meets architectural innovation and resource allocation. In CASES.","DOI":"10.1145\/2968455.2974013"},{"key":"e_1_2_1_5_1","unstructured":"D. Brooks and M. Martonosi. 2001. Dynamic thermal management for high-performance microprocessors. In HPCA.  D. Brooks and M. Martonosi. 2001. Dynamic thermal management for high-performance microprocessors. In HPCA."},{"key":"e_1_2_1_6_1","doi-asserted-by":"crossref","unstructured":"D. Calvo P. Gonz\u00e1lez L. D\u00edaz H. Posadas P. S\u00e1nchez E. Villar A. Acquaviva and E. Macii. 2011. A multi-processing systems-on-chip native simulation framework for power and thermal-aware design. JOLPE (2011).  D. Calvo P. Gonz\u00e1lez L. D\u00edaz H. Posadas P. S\u00e1nchez E. Villar A. Acquaviva and E. Macii. 2011. A multi-processing systems-on-chip native simulation framework for power and thermal-aware design. JOLPE (2011).","DOI":"10.1166\/jolpe.2011.1112"},{"key":"e_1_2_1_7_1","doi-asserted-by":"crossref","unstructured":"T. E. Carlson W. Heirman S. Eyerman I. Hur and L. Eeckhout. 2014. An evaluation of high-level mechanistic core models. TACO (2014).  T. E. Carlson W. Heirman S. Eyerman I. Hur and L. Eeckhout. 2014. An evaluation of high-level mechanistic core models. TACO (2014).","DOI":"10.1145\/2629677"},{"key":"e_1_2_1_8_1","doi-asserted-by":"crossref","unstructured":"K. Chen etal 2012. CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. In DATE.  K. Chen et al. 2012. CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. In DATE.","DOI":"10.1109\/DATE.2012.6176428"},{"key":"e_1_2_1_9_1","doi-asserted-by":"crossref","unstructured":"R. Cochran and S. Reda. 2013. Thermal prediction and adaptive control through workload phase detection. TODAES (2013).  R. Cochran and S. Reda. 2013. Thermal prediction and adaptive control through workload phase detection. TODAES (2013).","DOI":"10.1145\/2390191.2390198"},{"key":"e_1_2_1_10_1","doi-asserted-by":"crossref","unstructured":"A. K. Coskun T. S. Rosing and K. C Gross. 2008. Proactive temperature management in MPSoCs. In ISLPED.  A. K. Coskun T. S. Rosing and K. C Gross. 2008. Proactive temperature management in MPSoCs. In ISLPED.","DOI":"10.1145\/1393921.1393966"},{"key":"e_1_2_1_11_1","doi-asserted-by":"crossref","unstructured":"D. Cuesta J. Ayala J. Hidalgo M. Poncino A. Acquaviva and E. Macii. 2010. Thermal-aware floorplanning exploration for 3D multi-core architectures. In GLSVLSI.  D. Cuesta J. Ayala J. Hidalgo M. Poncino A. Acquaviva and E. Macii. 2010. Thermal-aware floorplanning exploration for 3D multi-core architectures. In GLSVLSI.","DOI":"10.1145\/1785481.1785505"},{"key":"e_1_2_1_12_1","doi-asserted-by":"crossref","unstructured":"K. Dev A. N. Nowroz and S. Reda. 2013. Power mapping and modeling of multi-core processors. In ISLPED.  K. Dev A. N. Nowroz and S. Reda. 2013. Power mapping and modeling of multi-core processors. In ISLPED.","DOI":"10.1109\/ISLPED.2013.6629264"},{"key":"e_1_2_1_13_1","doi-asserted-by":"crossref","unstructured":"A. Fourmigue G. Beltrame and G. Nicolescu. 2014. Efficient transient thermal simulation of 3D ICs with liquid-cooling and through silicon vias. In DATE.  A. Fourmigue G. Beltrame and G. Nicolescu. 2014. Efficient transient thermal simulation of 3D ICs with liquid-cooling and through silicon vias. In DATE.","DOI":"10.7873\/DATE.2014.087"},{"key":"e_1_2_1_14_1","doi-asserted-by":"crossref","unstructured":"M. H. Hajkazemi etal 2017. Heterogeneous HMC+DDRx memory management for performance-temperature tradeoffs. JETCS (Sept. 2017).  M. H. Hajkazemi et al. 2017. Heterogeneous HMC+DDRx memory management for performance-temperature tradeoffs. JETCS (Sept. 2017).","DOI":"10.1145\/3106233"},{"key":"e_1_2_1_15_1","doi-asserted-by":"crossref","unstructured":"F. Hameed M. A. A. Faruque and J. Henkel. 2011. Dynamic thermal management in 3D multi-core architecture through run-time adaptation. In DATE.  F. Hameed M. A. A. Faruque and J. Henkel. 2011. Dynamic thermal management in 3D multi-core architecture through run-time adaptation. In DATE.","DOI":"10.1109\/DATE.2011.5763053"},{"key":"e_1_2_1_16_1","volume-title":"SPEC CPU2006 benchmark descriptions. ACM SIGARCH Computer Architecture News","author":"Henning J. L.","year":"2006","unstructured":"J. L. Henning . 2006 . SPEC CPU2006 benchmark descriptions. ACM SIGARCH Computer Architecture News (2006). J. L. Henning. 2006. SPEC CPU2006 benchmark descriptions. ACM SIGARCH Computer Architecture News (2006)."},{"key":"e_1_2_1_17_1","volume-title":"RELOCATE: Register file local access pattern redistribution mechanism for power and thermal management in out-of-order embedded processor. In HiPEAC.","author":"Homayoun H.","year":"2010","unstructured":"H. Homayoun , A. Gupta , A. Veidenbaum , A. Sasan , F. Kurdahi , and N. Dutt . 2010 . RELOCATE: Register file local access pattern redistribution mechanism for power and thermal management in out-of-order embedded processor. In HiPEAC. H. Homayoun, A. Gupta, A. Veidenbaum, A. Sasan, F. Kurdahi, and N. Dutt. 2010. RELOCATE: Register file local access pattern redistribution mechanism for power and thermal management in out-of-order embedded processor. In HiPEAC."},{"key":"e_1_2_1_18_1","doi-asserted-by":"crossref","unstructured":"H. Huang K. G. Shin C. Lefurgy and T. Keller. 2005. Improving energy efficiency by making DRAM less randomly accessed. In ISLPED.  H. Huang K. G. Shin C. Lefurgy and T. Keller. 2005. Improving energy efficiency by making DRAM less randomly accessed. In ISLPED.","DOI":"10.1145\/1077603.1077696"},{"key":"e_1_2_1_19_1","doi-asserted-by":"crossref","unstructured":"J. Jeddeloh and B. Keeth. 2012. Hybrid memory cube new DRAM architecture increases density and performance. In VLSIT.  J. Jeddeloh and B. Keeth. 2012. Hybrid memory cube new DRAM architecture increases density and performance. In VLSIT.","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"e_1_2_1_20_1","doi-asserted-by":"crossref","unstructured":"D. Juan etal 2014. Statistical peak temperature prediction and thermal yield improvement for 3D chip multiprocessors. TODAES (2014).  D. Juan et al. 2014. Statistical peak temperature prediction and thermal yield improvement for 3D chip multiprocessors. TODAES (2014).","DOI":"10.1145\/2633606"},{"key":"e_1_2_1_21_1","doi-asserted-by":"crossref","unstructured":"D. Juan H. Zhou D. Marculescu and X. Li. 2012. A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors. In ASPDAC.  D. Juan H. Zhou D. Marculescu and X. Li. 2012. A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors. In ASPDAC.","DOI":"10.1109\/ASPDAC.2012.6165027"},{"key":"e_1_2_1_22_1","doi-asserted-by":"crossref","unstructured":"P. Kumar and D. Atienza. 2010. Neural network based on-chip thermal simulator. In ISCAS.  P. Kumar and D. Atienza. 2010. Neural network based on-chip thermal simulator. In ISCAS.","DOI":"10.1109\/ISCAS.2010.5537439"},{"key":"e_1_2_1_23_1","doi-asserted-by":"crossref","unstructured":"D. Lee S. Das J. R. Doppa P. P. Pande and K. Chakrabarty. 2018. Performance and thermal tradeoffs for energy-efficient monolithic 3D network-on-chip. TODAES (2018).  D. Lee S. Das J. R. Doppa P. P. Pande and K. Chakrabarty. 2018. Performance and thermal tradeoffs for energy-efficient monolithic 3D network-on-chip. TODAES (2018).","DOI":"10.1145\/3223046"},{"key":"e_1_2_1_24_1","doi-asserted-by":"crossref","unstructured":"C. H. Liao C. H. P. Wen and K. Chakrabarty. 2015. An online thermal-constrained task scheduler for 3D multi-core processors. In DATE\u201915.  C. H. Liao C. H. P. Wen and K. Chakrabarty. 2015. An online thermal-constrained task scheduler for 3D multi-core processors. In DATE\u201915.","DOI":"10.7873\/DATE.2015.0724"},{"key":"e_1_2_1_25_1","doi-asserted-by":"crossref","unstructured":"W. Liu L. Yang W. Jiang L. Feng N. Guan W. Zhang and N. Dutt. 2018. Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip. TC (2018).  W. Liu L. Yang W. Jiang L. Feng N. Guan W. Zhang and N. Dutt. 2018. Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip. TC (2018).","DOI":"10.1109\/TC.2018.2844365"},{"key":"e_1_2_1_26_1","doi-asserted-by":"crossref","unstructured":"W. Lo etal 2016. Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC). In DATE.  W. Lo et al. 2016. Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC). In DATE.","DOI":"10.3850\/9783981537079_0046"},{"key":"e_1_2_1_27_1","doi-asserted-by":"crossref","unstructured":"G. L. Loi etal 2006. A thermally-aware performance analysis of vertically integrated (3D) processor-memory hierarchy. In DAC.  G. L. Loi et al. 2006. A thermally-aware performance analysis of vertically integrated (3D) processor-memory hierarchy. In DAC.","DOI":"10.1145\/1146909.1147160"},{"key":"e_1_2_1_28_1","doi-asserted-by":"crossref","unstructured":"Y. Lu etal 2016. Rank-aware dynamic migrations and adaptive demotions for DRAM power management. TC (2016).  Y. Lu et al. 2016. Rank-aware dynamic migrations and adaptive demotions for DRAM power management. TC (2016).","DOI":"10.1109\/TC.2015.2409847"},{"key":"e_1_2_1_29_1","doi-asserted-by":"crossref","unstructured":"J. Meng etal 2012. Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints. In DAC.  J. Meng et al. 2012. Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints. In DAC.","DOI":"10.1145\/2228360.2228477"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.5555\/1953048.2078195"},{"key":"e_1_2_1_31_1","doi-asserted-by":"crossref","unstructured":"L. Siddhu and P. R. Panda. 2019. FastCool: Leakage aware dynamic thermal management of 3D memories. In DATE.  L. Siddhu and P. R. Panda. 2019. FastCool: Leakage aware dynamic thermal management of 3D memories. In DATE.","DOI":"10.23919\/DATE.2019.8715091"},{"key":"e_1_2_1_32_1","doi-asserted-by":"crossref","unstructured":"G. Singla G. Kaur A. K. Unver and U. Y. Ogras. 2015. Predictive dynamic thermal and power management for heterogeneous mobile platforms. In DATE.  G. Singla G. Kaur A. K. Unver and U. Y. Ogras. 2015. Predictive dynamic thermal and power management for heterogeneous mobile platforms. In DATE.","DOI":"10.7873\/DATE.2015.1036"},{"key":"e_1_2_1_33_1","doi-asserted-by":"crossref","unstructured":"F. Sironi M. Maggio R. Cattaneo G. F. D. Nero D. Sciuto and M. D. Santambrogio. 2013. ThermOS: System support for dynamic thermal management of chip multi-processors. In PACT.  F. Sironi M. Maggio R. Cattaneo G. F. D. Nero D. Sciuto and M. D. Santambrogio. 2013. ThermOS: System support for dynamic thermal management of chip multi-processors. In PACT.","DOI":"10.1109\/PACT.2013.6618802"},{"key":"e_1_2_1_34_1","volume-title":"LIBRA: Thermal and process variation aware reliability management in photonic networks-on-chip. TMSCS","author":"Thakkar I. G.","year":"2018","unstructured":"I. G. Thakkar , S. Pasricha , 2018 . LIBRA: Thermal and process variation aware reliability management in photonic networks-on-chip. TMSCS (2018). I. G. Thakkar, S. Pasricha, et al. 2018. LIBRA: Thermal and process variation aware reliability management in photonic networks-on-chip. TMSCS (2018)."},{"key":"e_1_2_1_35_1","doi-asserted-by":"crossref","unstructured":"S. Xydis G. Palermo and C. Silvano. 2013. Thermal-aware datapath merging for coarse-grained reconfigurable processors. In DATE.  S. Xydis G. Palermo and C. Silvano. 2013. Thermal-aware datapath merging for coarse-grained reconfigurable processors. In DATE.","DOI":"10.7873\/DATE.2013.334"},{"key":"e_1_2_1_36_1","volume-title":"System-level modeling and analysis of thermal effects in WDM-based optical networks-on-chip. TCAD","author":"Ye Y.","year":"2014","unstructured":"Y. Ye , Z. Wang , P. Yang , J. Xu , X. Wu , X. Wang , M. Nikdast , Z. Wang , and L. H. K. Duong . 2014. System-level modeling and analysis of thermal effects in WDM-based optical networks-on-chip. TCAD ( 2014 ). Y. Ye, Z. Wang, P. Yang, J. Xu, X. Wu, X. Wang, M. Nikdast, Z. Wang, and L. H. K. Duong. 2014. System-level modeling and analysis of thermal effects in WDM-based optical networks-on-chip. TCAD (2014)."},{"key":"e_1_2_1_37_1","doi-asserted-by":"crossref","unstructured":"M. Zapater etal 2013. Leakage and temperature aware server control for improving energy efficiency in data centers. In DATE.  M. Zapater et al. 2013. Leakage and temperature aware server control for improving energy efficiency in data centers. In DATE.","DOI":"10.7873\/DATE.2013.067"},{"key":"e_1_2_1_38_1","doi-asserted-by":"crossref","unstructured":"K. Zhang A. Guliani S. Ogrenci-Memik G. Memik K. Yoshii R. Sankaran and P. Beckman. 2018. Machine learning-based temperature prediction for runtime thermal management across system components. TPDS (2018).  K. Zhang A. Guliani S. Ogrenci-Memik G. Memik K. Yoshii R. Sankaran and P. Beckman. 2018. Machine learning-based temperature prediction for runtime thermal management across system components. TPDS (2018).","DOI":"10.1109\/TPDS.2017.2732951"},{"key":"e_1_2_1_39_1","unstructured":"R. Zhang M. R. Stan and K. Skadron. 2015. HotSpot 6.0: Validation acceleration and extension. (2015).  R. Zhang M. R. Stan and K. Skadron. 2015. HotSpot 6.0: Validation acceleration and extension. (2015)."},{"key":"e_1_2_1_40_1","doi-asserted-by":"crossref","unstructured":"Z. Zhao A. Gerstlauer and L. K. John. 2017. Source-level performance energy reliability power and thermal (PERPT) simulation. TCAD (2017).  Z. Zhao A. Gerstlauer and L. K. John. 2017. Source-level performance energy reliability power and thermal (PERPT) simulation. TCAD (2017).","DOI":"10.1109\/TCAD.2016.2578882"},{"key":"e_1_2_1_41_1","doi-asserted-by":"crossref","unstructured":"J. Zheng N. Wu L. Zhou Y. Ye and K. Sun. 2016. DFSB-based thermal management scheme for 3D NoC-bus architectures. TVLSI (2016).  J. Zheng N. Wu L. Zhou Y. Ye and K. Sun. 2016. DFSB-based thermal management scheme for 3D NoC-bus architectures. TVLSI (2016).","DOI":"10.1109\/TVLSI.2015.2439698"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3358208","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3358208","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:23:07Z","timestamp":1750202587000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3358208"}},"subtitle":["Leakage Aware Thermal Management for 3D Memories Using a Lightweight Temperature Predictor"],"short-title":[],"issued":{"date-parts":[[2019,10,8]]},"references-count":41,"journal-issue":{"issue":"5s","published-print":{"date-parts":[[2019,10,31]]}},"alternative-id":["10.1145\/3358208"],"URL":"https:\/\/doi.org\/10.1145\/3358208","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2019,10,8]]},"assertion":[{"value":"2019-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-10-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}