{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:27:08Z","timestamp":1750220828392,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,10,9]],"date-time":"2019-10-09T00:00:00Z","timestamp":1570579200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,10,9]]},"DOI":"10.1145\/3359986.3361205","type":"proceedings-article","created":{"date-parts":[[2019,10,7]],"date-time":"2019-10-07T12:21:06Z","timestamp":1570450866000},"page":"1-10","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Polyhedral fragments"],"prefix":"10.1145","author":[{"given":"Michael","family":"Witterauf","sequence":"first","affiliation":[{"name":"Friedrich-Alexander-Universit\u00e4t, Erlangen-N\u00fcrnberg"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Frank","family":"Hannig","sequence":"additional","affiliation":[{"name":"Friedrich-Alexander-Universit\u00e4t, Erlangen-N\u00fcrnberg"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J\u00fcrgen","family":"Teich","sequence":"additional","affiliation":[{"name":"Friedrich-Alexander-Universit\u00e4t, Erlangen-N\u00fcrnberg"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,10,9]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","first-page":"53","DOI":"10.1007\/978-1-4020-8588-8_4","volume-title":"High-level synthesis: From algorithm to digital circuit","author":"Aditya S.","year":"2008","unstructured":"S. Aditya and V. Kathail, High-level synthesis: From algorithm to digital circuit. Dordrecht: Springer Netherlands, 2008, ch. Algorithmic Synthesis Using PICO, pp. 53--74."},{"key":"e_1_3_2_1_2_1","unstructured":"D. Kissler F. Hannig A. Kupriyanov and J. Teich \"A dynamically reconfigurable weakly programmable processor array architecture template.\" in Proceedings of the 2nd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC) 2006 pp. 31--37."},{"issue":"4","key":"e_1_3_2_1_3_1","first-page":"133","article-title":"Invasive tightly-coupled processor arrays: A domain-specific architecture\/compiler co-design approach","volume":"13","author":"Hannig F.","year":"2014","unstructured":"F. Hannig, V. Lari, S. Boppu, A. Tanase, and O. Reiche, \"Invasive tightly-coupled processor arrays: A domain-specific architecture\/compiler co-design approach,\" ACM Transactions on Embedded Computing Systems (TECS), vol. 13, no. 4s, p. 133, 2014.","journal-title":"ACM Transactions on Embedded Computing Systems (TECS)"},{"key":"e_1_3_2_1_4_1","first-page":"5","volume-title":"Orthogonal instruction processing: An alternative to lightweight VLIW processors,\" in IEEE 11th International Symposium on Embedded Multicore\/Many-core Systems-on-Chip (MCSoC)","author":"Brand M.","year":"2017","unstructured":"M. Brand, F. Hannig, A. Tanase, and J. Teich, \"Orthogonal instruction processing: An alternative to lightweight VLIW processors,\" in IEEE 11th International Symposium on Embedded Multicore\/Many-core Systems-on-Chip (MCSoC), 2017, pp. 5--12."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/49418"},{"key":"e_1_3_2_1_6_1","volume-title":"dissertation","author":"Rao S. K.","year":"1985","unstructured":"S. K. Rao, \"Regular iterative algorithms and their implementation on processor arrays,\" Ph.D. dissertation, Stanford University, 1985."},{"key":"e_1_3_2_1_7_1","first-page":"131","volume-title":"Architectures and Processors (ASAP)","author":"Teich J.","year":"1996","unstructured":"J. Teich, L. Thiele, and L. Zhang, \"Scheduling of partitioned regular algorithms on processor arrays with constrained resources,\" in 1996 IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 1996, pp. 131--144."},{"key":"e_1_3_2_1_8_1","volume-title":"Scheduling techniques for high-throughput loop accelerators","author":"Hannig F.","year":"2009","unstructured":"F. Hannig, Scheduling techniques for high-throughput loop accelerators. Munich: Verlag Dr. Hut, 2009."},{"key":"e_1_3_2_1_9_1","volume-title":"A compiler for application specific processor arrays","author":"Teich J.","year":"1993","unstructured":"J. Teich, A compiler for application specific processor arrays. Aachen: Shaker, 1993."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01602099"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1014192.802449"},{"key":"e_1_3_2_1_12_1","first-page":"58","volume-title":"Architectures and Processors (ASAP)","author":"Witterauf M.","year":"2016","unstructured":"M. Witterauf, A. Tanase, F. Hannig, and J. Teich, \"Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays,\" in 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2016, pp. 58--66."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-014-0891-2"},{"key":"e_1_3_2_1_14_1","first-page":"10","volume-title":"Architectures and Processors","author":"Boppu S.","year":"2013","unstructured":"S. Boppu, F. Hannig, \"Loop program mapping and compact code generation for programmable hardware accelerators,\" in 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, June 2013, pp. 10--17."},{"key":"e_1_3_2_1_15_1","first-page":"1","volume-title":"DynTile: Parametric tiled loop generation for parallel execution on multicore processors,\" in IEEE International Symposium on Parallel Distributed Processing (IPDPS)","author":"Hartono A.","year":"2010","unstructured":"A. Hartono, M. M. Baskaran, J. Ramanujam, and P. Sadayappan, \"DynTile: Parametric tiled loop generation for parallel execution on multicore processors,\" in IEEE International Symposium on Parallel Distributed Processing (IPDPS), 2010, pp. 1--12."},{"key":"e_1_3_2_1_16_1","first-page":"293","volume-title":"Efficient tiled loop generation: D-tiling,\" in Languages and compilers for parallel computing (LCPC)","author":"Kim D.","year":"2009","unstructured":"D. Kim and S. Rajopadhye, \"Efficient tiled loop generation: D-tiling,\" in Languages and compilers for parallel computing (LCPC). Springer, 2009, pp. 293--307."},{"key":"e_1_3_2_1_17_1","first-page":"127","volume-title":"ACM","author":"Kong M.","year":"2013","unstructured":"M. Kong, R. Veras, K. Stock, F. Franchetti, L.-N. Pouchet, and P. Sadayappan, \"When polyhedral transformations meet SIMD code generation,\" in ACM Sigplan Notices, vol. 48, no. 6. ACM, 2013, pp. 127--138."},{"key":"e_1_3_2_1_18_1","first-page":"136","volume-title":"Parametric GPU code generation for affine loop programs,\" in Languages and compilers for parallel computing (LCPC)","author":"Konstantinidis A.","year":"2014","unstructured":"A. Konstantinidis, P. Kelly, J. Ramanujam, and P. Sadayappan, \"Parametric GPU code generation for affine loop programs,\" in Languages and compilers for parallel computing (LCPC), vol. 8664. Springer, 2014, pp. 136--151."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-013-0259-4"},{"key":"e_1_3_2_1_20_1","first-page":"225","volume-title":"Code bones: Fast and flexible code generation for dynamic and speculative polyhedral optimization,\" in Proceedings of the 22nd European Conference on Parallel Processing (Euro-Par)","author":"Caama\u00f1o J. M. M.","year":"2016","unstructured":"J. M. M. Caama\u00f1o, W. Wolff, and P. Clauss, \"Code bones: Fast and flexible code generation for dynamic and speculative polyhedral optimization,\" in Proceedings of the 22nd European Conference on Parallel Processing (Euro-Par). Springer, 2016, pp. 225--237."}],"event":{"name":"MEMOCODE '19: 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA"],"location":"La Jolla California","acronym":"MEMOCODE '19"},"container-title":["Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3359986.3361205","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3359986.3361205","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:13:27Z","timestamp":1750202007000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3359986.3361205"}},"subtitle":["an efficient representation for symbolically generating code for processor arrays"],"short-title":[],"issued":{"date-parts":[[2019,10,9]]},"references-count":20,"alternative-id":["10.1145\/3359986.3361205","10.1145\/3359986"],"URL":"https:\/\/doi.org\/10.1145\/3359986.3361205","relation":{},"subject":[],"published":{"date-parts":[[2019,10,9]]},"assertion":[{"value":"2019-10-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}