{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,24]],"date-time":"2026-08-24T00:24:53Z","timestamp":1787531093680,"version":"build-2736575974"},"reference-count":42,"publisher":"Association for Computing Machinery (ACM)","issue":"6","license":[{"start":{"date-parts":[[2019,11,15]],"date-time":"2019-11-15T00:00:00Z","timestamp":1573776000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Department of Science and Technology, India"},{"name":"DST-FIST program","award":["2016"],"award-info":[{"award-number":["2016"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2019,11,30]]},"abstract":"<jats:p>Illegal use of memory pointers is a serious security vulnerability. A large number of malwares exploit the spatial and temporal nature of these vulnerabilities to subvert execution or glean sensitive data from an application. Recent countermeasures attach metadata to memory pointers, which define the pointer\u2019s capabilities. The metadata is used by the hardware to validate pointer-based memory accesses. However, recent works have considerable overheads. Further, the pointer validation is decoupled from the actual memory access. We show that this could open up vulnerabilities in multithreaded applications and introduce new vulnerabilities due to speculation in out-of-order processors.<\/jats:p>\n          <jats:p>In this article, we demonstrate that the overheads can be reduced considerably by efficient metadata management. We show that the hardware can be designed in a manner that would remain safe in multithreaded applications and immune to speculative vulnerabilities. We achieve these by ensuring that the pointer validations and the corresponding memory access is always done atomically and in order. To evaluate our scheme, which we call ALEXIA, we enhance an OpenRISC processor to perform the memory validation at runtime and also add compiler support. ALEXIA is the first hardware countermeasure scheme for memory protection that provides such an end-to-end solution. We evaluate the processor on an Altera FPGA and show that the runtime overhead, on average, is 14%, with negligible impact on the processor\u2019s size and clock frequency. There is also a negligible impact on the program\u2019s code and data sizes.<\/jats:p>","DOI":"10.1145\/3362064","type":"journal-article","created":{"date-parts":[[2019,11,15]],"date-time":"2019-11-15T21:16:57Z","timestamp":1573852617000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["ALEXIA"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3817-1548","authenticated-orcid":false,"given":"Gnanambikai","family":"Krishnakumar","sequence":"first","affiliation":[{"name":"Indian Institute of Technology, Madras, Chennai, Tamilnadu, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kommuru Alekhya","family":"REDDY","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology, Madras, Chennai, Tamilnadu, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chester","family":"Rebeiro","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology, Madras, Chennai, Tamilnadu, India"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,11,15]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"2001. 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