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Syst."],"published-print":{"date-parts":[[2019,11,30]]},"abstract":"<jats:p>\n            Shared last level caches (LLC) of multicore systems-on-chip are subject to a significant amount of contention over a limited bandwidth, resulting in major performance bottlenecks that make the issue a first-order concern in modern multiprocessor systems-on-chip. Even though shared cache space partitioning has been extensively studied in the past, the problem of cache bandwidth partitioning has not received sufficient attention. We demonstrate the occurrence of such contention and the resulting impact on the overall system performance. To address the issue, we perform detailed simulations to study the impact of different parameters and propose a novel cache bandwidth partitioning technique, called\n            <jats:italic>REAL<\/jats:italic>\n            , that arbitrates among cache access requests originating from different processor cores. It monitors the LLC access patterns to dynamically assign a priority value to each core. Experimental results on different mixes of benchmarks show up to 2.13\u00d7 overall system speedup over baseline policies, with minimal impact on energy.\n          <\/jats:p>","DOI":"10.1145\/3362100","type":"journal-article","created":{"date-parts":[[2019,11,15]],"date-time":"2019-11-15T21:16:57Z","timestamp":1573852617000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["REAL"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0827-2882","authenticated-orcid":false,"given":"Sakshi","family":"Tiwari","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Delhi, New Delhi, India"}]},{"given":"Shreshth","family":"Tuli","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Delhi, New Delhi, India"}]},{"given":"Isaar","family":"Ahmad","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Delhi, New Delhi, India"}]},{"given":"Ayushi","family":"Agarwal","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Delhi, New Delhi, India"}]},{"given":"Preeti Ranjan","family":"Panda","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Delhi, New Delhi, India"}]},{"given":"Sreenivas","family":"Subramoney","sequence":"additional","affiliation":[{"name":"Microarchitecture Research Lab, Intel, Bengaluru, India"}]}],"member":"320","published-online":{"date-parts":[[2019,11,15]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2015.7108452"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/3085572"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555792"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"volume-title":"InProceedings of the 33rd International Symposium on Computer Architecture (ISCA\u201906)","author":"Chang Jichuan","key":"e_1_2_1_5_1"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815976"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-017-9285-4"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346180"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2013.61"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2428694"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/384285.379253"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555779"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382172"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0083"},{"volume-title":"Keckler","year":"2002","author":"Kim Changkyu","key":"e_1_2_1_15_1"},{"volume-title":"Proceedings of the 16th International Symposium on High-Performance Computer Architecture. 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IEEE Computer Society, 208--222","author":"Nesbit Kyle J.","key":"e_1_2_1_24_1"},{"volume-title":"Proceedings of the 39th IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201906)","author":"Moinuddin","key":"e_1_2_1_25_1"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339668"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342112"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815972"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830803"},{"key":"e_1_2_1_30_1","unstructured":"Richard S. Sutton Andrew G. Barto etal 1998. Introduction to Reinforcement Learning Vol. 2. MIT press Cambridge.  Richard S. Sutton Andrew G. Barto et al. 1998. Introduction to Reinforcement Learning Vol. 2. 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