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Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2020,1,31]]},"abstract":"<jats:p>\n            This article describes a diagnosis-aware hybrid concurrent error detection (\n            <jats:italic>DAH-CED<\/jats:italic>\n            ) scheme that can facilitate both off-line and on-line test applications. By using the proposed scheme, not only the probability of detecting errors (on-line) but also the diagnosability of the target circuit (off-line) can be significantly enhanced. The proposed scheme combines the implication-based method with the parity check method. In particular, novel algorithms are developed to identify specific implications for enhancing the diagnosability for the modeled faults proactively. Furthermore, a reduction algorithm is also presented to minimize the number of the employed implications, while no loss on probability of detecting errors and diagnosability is also guaranteed. To the best of our knowledge, this issue is not addressed in the literature. To validate the proposed scheme, not only stuck-at faults but also transition faults are considered to simulate the timing-related errors. The experimental results on nine ITC\u201999 benchmark circuits show that the diagnosability for stuck-at (transition) faults is enhanced by 6.88% (7.78%) by applying the proposed scheme. As for the probability of detecting errors, 97.73% (97.10%) is achieved for errors caused by stuck-at (transition) faults. Moreover, only 3.11% of implications are needed.\n          <\/jats:p>","DOI":"10.1145\/3364681","type":"journal-article","created":{"date-parts":[[2019,11,22]],"date-time":"2019-11-22T18:41:47Z","timestamp":1574448107000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["An Implication-based Test Scheme for Both Diagnosis and Concurrent Error Detection Applications"],"prefix":"10.1145","volume":"25","author":[{"given":"Chih-Hao","family":"Wang","sequence":"first","affiliation":[{"name":"National Sun Yat-sen University, Kaohsiung, Taiwan, R.O.C"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tong-Yu","family":"Hsieh","sequence":"additional","affiliation":[{"name":"National Sun Yat-sen University, Kaohsiung, Taiwan, R.O.C"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,11,22]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.153"},{"volume-title":"Proceedings of the 2000 IEEE International Test Conference (ITC\u201900)","author":"Mitra Subhasish","key":"e_1_2_1_2_1","unstructured":"Subhasish Mitra and Edward J . McCluskey. 2000. Which concurrent error detection scheme to choose? In Proceedings of the 2000 IEEE International Test Conference (ITC\u201900) . 985--994. Subhasish Mitra and Edward J. McCluskey. 2000. Which concurrent error detection scheme to choose? In Proceedings of the 2000 IEEE International Test Conference (ITC\u201900). 985--994."},{"key":"e_1_2_1_3_1","volume-title":"Touba","author":"Wang Laung-Terng","year":"2008","unstructured":"Laung-Terng Wang , Charles E. Stroud , and Nur A . Touba . 2008 . System on Chip Test Architectures, Morgan Kaufmann . Laung-Terng Wang, Charles E. Stroud, and Nur A. Touba. 2008. System on Chip Test Architectures, Morgan Kaufmann."},{"key":"e_1_2_1_4_1","article-title":"Logic synthesis of multilevel circuits with concurrent error detection","volume":"16","author":"Touba Nur A.","year":"1997","unstructured":"Nur A. Touba and Edward J. McCluskey . 1997 . Logic synthesis of multilevel circuits with concurrent error detection . IEEE Trans. Comput-Aid. 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