{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,3]],"date-time":"2026-07-03T14:41:18Z","timestamp":1783089678344,"version":"3.54.6"},"reference-count":21,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2019,11,25]],"date-time":"2019-11-25T00:00:00Z","timestamp":1574640000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Key Research and Development Program of China","award":["2016YFB0201304"],"award-info":[{"award-number":["2016YFB0201304"]}]},{"name":"State Key Lab. of ASIC and System","award":["2018MS005"],"award-info":[{"award-number":["2018MS005"]}]},{"name":"the Laboratory of Mathematics for Nonlinear Science at Fudan University"},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["61874032,61574046, 61774045, 61574044, 61929102, 91730303 and 91330201"],"award-info":[{"award-number":["61874032,61574046, 61774045, 61574044, 61929102, 91730303 and 91330201"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2020,1,31]]},"abstract":"<jats:p>Tunable analog\/RF circuit has emerged as a promising technique to address the significant performance uncertainties caused by process variations. To optimize these tunable circuits after fabrication, most existing post-silicon programming methods are developed by using real-valued performance metrics. However, when measuring a performance of interest on silicon, it is often substantially more expensive to obtain a real-valued measurement than a binary testing outcome (i.e., pass or fail). In this article, we propose a Gaussian Process Classification model to capture the binary performance metrics of tunable analog\/RF circuits. Based on these models, post-silicon programming is cast into an optimization problem that can be solved by a novel Bayesian optimization algorithm. Moreover, measurement noises are further incorporated into our proposed post-silicon programming to produce a robust circuit. Two circuit examples demonstrate that the proposed approach can efficiently program tunable circuits with binary performance metrics while other conventional methods are not applicable.<\/jats:p>","DOI":"10.1145\/3365577","type":"journal-article","created":{"date-parts":[[2019,11,25]],"date-time":"2019-11-25T13:19:46Z","timestamp":1574687986000},"page":"1-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Analog\/RF Post-silicon Tuning via Bayesian Optimization"],"prefix":"10.1145","volume":"25","author":[{"given":"Renjian","family":"Pan","sequence":"first","affiliation":[{"name":"Fudan University, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jun","family":"Tao","sequence":"additional","affiliation":[{"name":"Fudan University, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yangfeng","family":"Su","sequence":"additional","affiliation":[{"name":"Fudan University, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dian","family":"Zhou","sequence":"additional","affiliation":[{"name":"University of Texas at Dallas, Richardson, TX"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"Fudan University, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xin","family":"Li","sequence":"additional","affiliation":[{"name":"Duke Kunshan University, Kunshan, Jiangsu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,11,25]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2001.929760"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.889371"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882513"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2106850"},{"key":"e_1_2_1_5_1","article-title":"An efficient Bayesian optimization approach for automated optimization of analog circuits","author":"Lyu W.","year":"2018","unstructured":"W. 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In Proceedings of the IEEE Custom Integrated Circuits Conference. G. Keskin, J. Proesel, and L. Pileggi. 2010. Statistical modeling and post manufacturing configuration for scaled analog CMOS. In Proceedings of the IEEE Custom Integrated Circuits Conference."},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the International Conference on Computer-Aided Design. 795--802","author":"Li X.","unstructured":"X. Li , F. Wang , S. Sun , and C. Gu . 2013. Bayesian model fusion: A statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits . In Proceedings of the International Conference on Computer-Aided Design. 795--802 . X. Li, F. Wang, S. Sun, and C. Gu. 2013. Bayesian model fusion: A statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits. In Proceedings of the International Conference on Computer-Aided Design. 795--802."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2014.2343192"},{"key":"e_1_2_1_13_1","volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference. 256--261","author":"Tao J.","unstructured":"J. Tao , Y. Wang , M. Jun , X. Li , R. Negi , T. Mukherjee , and L. Pileggi . 2014. Toward efficient programming of reconfigurable radio frequency (RF) receivers . In Proceedings of the Asia and South Pacific Design Automation Conference. 256--261 . J. Tao, Y. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee, and L. Pileggi. 2014. Toward efficient programming of reconfigurable radio frequency (RF) receivers. In Proceedings of the Asia and South Pacific Design Automation Conference. 256--261."},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the IEEE VLSI Test Symposium. 299--308","author":"Biswas S.","unstructured":"S. Biswas and R. Blanton . 2008. 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