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Thus, present embedded systems are designed with MPSoCs, and one possible way MPSoCs can be realized is through Pipelined MPSoC (PMPSoC) architectures, which are used in applications from video surveillance to cryptosystems. Hardware Trojans (HTs) on PMPSoCs are a significant concern due to the damage caused by their stealth. An adversary could use HTs to extract secret information (data leakage) to modify functionality\/data (functional modification) or make PMPSoCs deny service. In this article, we present PMPGuard, a mechanism that (1) detects the presence of hardware Trojans in Third Party Intellectual Property (3PIP) cores of PMPSoCs by continuous monitoring and testing and (2) recovers the system by switching the infected processor core with another one. We designed, implemented, and tested the system on a commercial cycle accurate multiprocessor simulation environment. Compared to the state-of-the-art system-level techniques that use Triple Modular Redundancy (TMR) and therefore incur at least 3\u00d7 area and power overheads, our proposed system incurs about 2\u00d7 area and 1.5\u00d7 power overheads without any adverse impact on throughput.<\/jats:p>","DOI":"10.1145\/3365578","type":"journal-article","created":{"date-parts":[[2020,1,16]],"date-time":"2020-01-16T03:52:07Z","timestamp":1579146727000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Hardware Trojan Mitigation in Pipelined MPSoCs"],"prefix":"10.1145","volume":"25","author":[{"given":"Amin","family":"Malekpour","sequence":"first","affiliation":[{"name":"University of New South Wales, Sydney, NSW, Australia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roshan","family":"Ragel","sequence":"additional","affiliation":[{"name":"University of Peradeniya, SriLanka"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tuo","family":"Li","sequence":"additional","affiliation":[{"name":"University of New South Wales, Sydney, NSW, Australia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haris","family":"Javaid","sequence":"additional","affiliation":[{"name":"Xilinx, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aleksandar","family":"Ignjatovic","sequence":"additional","affiliation":[{"name":"University of New South Wales, Sydney, NSW, Australia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sri","family":"Parameswaran","sequence":"additional","affiliation":[{"name":"University of New South Wales, Sydney, NSW, Australia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,1,15]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1145\/1558607.1558671"},{"doi-asserted-by":"publisher","key":"e_1_2_1_2_1","DOI":"10.1145\/1687399.1687426"},{"doi-asserted-by":"publisher","key":"e_1_2_1_3_1","DOI":"10.1109\/MDT.2010.24"},{"doi-asserted-by":"publisher","key":"e_1_2_1_5_1","DOI":"10.1109\/DATE.2012.6176642"},{"doi-asserted-by":"publisher","key":"e_1_2_1_6_1","DOI":"10.1109\/MDT.2012.2196252"},{"doi-asserted-by":"publisher","key":"e_1_2_1_7_1","DOI":"10.1016\/j.cose.2009.03.002"},{"doi-asserted-by":"publisher","key":"e_1_2_1_8_1","DOI":"10.1109\/HLDVT.2009.5340158"},{"doi-asserted-by":"publisher","key":"e_1_2_1_9_1","DOI":"10.1109\/TETC.2017.2654268"},{"doi-asserted-by":"publisher","key":"e_1_2_1_10_1","DOI":"10.1145\/2593069.2593150"},{"doi-asserted-by":"publisher","key":"e_1_2_1_11_1","DOI":"10.5555\/1870926.1871135"},{"doi-asserted-by":"publisher","key":"e_1_2_1_12_1","DOI":"10.1109\/MDAT.2017.2766170"},{"doi-asserted-by":"publisher","key":"e_1_2_1_13_1","DOI":"10.1016\/j.micpro.2009.02.010"},{"doi-asserted-by":"publisher","key":"e_1_2_1_14_1","DOI":"10.1145\/3014166"},{"doi-asserted-by":"publisher","key":"e_1_2_1_15_1","DOI":"10.1109\/TDSC.2017.2654352"},{"volume-title":"SPEC CPU2006 benchmark descriptions. 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