{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,13]],"date-time":"2025-11-13T18:25:47Z","timestamp":1763058347266,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,1,15]],"date-time":"2020-01-15T00:00:00Z","timestamp":1579046400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,1,15]]},"DOI":"10.1145\/3368474.3368476","type":"proceedings-article","created":{"date-parts":[[2019,12,17]],"date-time":"2019-12-17T13:31:42Z","timestamp":1576589502000},"page":"131-141","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["On the Correct Measurement of Application Memory Bandwidth and Memory Access Latency"],"prefix":"10.1145","author":[{"given":"Christian","family":"Helm","sequence":"first","affiliation":[{"name":"The University of Tokyo, Tokyo, Japan"}]},{"given":"Kenjiro","family":"Taura","sequence":"additional","affiliation":[{"name":"The University of Tokyo, Tokyo, Japan"}]}],"member":"320","published-online":{"date-parts":[[2020,1,15]]},"reference":[{"key":"e_1_3_2_1_1_1","series-title":"Lecture Notes in Computer Science 8384 LNCS","volume-title":"Monitoring performance and power for application characterization with the cache-aware roofline model","author":"Ant\u00e3o D.","year":"2014","unstructured":"Ant\u00e3o , D. , Tani\u00e7a , L. , Ilic , A. , Pratas , F. , Tom\u00e1s , P. , and Sousa , L . Monitoring performance and power for application characterization with the cache-aware roofline model . Lecture Notes in Computer Science 8384 LNCS ( 2014 ), 747--760. Ant\u00e3o, D., Tani\u00e7a, L., Ilic, A., Pratas, F., Tom\u00e1s, P., and Sousa, L. Monitoring performance and power for application characterization with the cache-aware roofline model. Lecture Notes in Computer Science 8384 LNCS (2014), 747--760."},{"key":"e_1_3_2_1_3_1","volume-title":"Inside Intel Core Microarchitecture and Smart Memory Access. Tech. rep","author":"Dowek J.","year":"2006","unstructured":"Dowek , J. Inside Intel Core Microarchitecture and Smart Memory Access. Tech. rep ., Intel Corporation , 2006 . Dowek, J. Inside Intel Core Microarchitecture and Smart Memory Access. Tech. rep., Intel Corporation, 2006."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1353522.1353531"},{"key":"e_1_3_2_1_5_1","volume-title":"Kerncraft: A Tool for Analytic Performance Modeling of Loop Kernels. Tools for High Performance Computing","author":"Hammer J.","year":"2016","unstructured":"Hammer , J. , Eitzinger , J. , Hager , G. , and Wellein , G . Kerncraft: A Tool for Analytic Performance Modeling of Loop Kernels. Tools for High Performance Computing ( 2016 ). Hammer, J., Eitzinger, J., Hager, G., and Wellein, G. Kerncraft: A Tool for Analytic Performance Modeling of Loop Kernels. Tools for High Performance Computing (2016)."},{"key":"e_1_3_2_1_6_1","volume-title":"PerfMemPlus: A Tool for Automatic Discovery of Memory Performance Problems. In 34th International Conference, ISC High Performance","author":"Helm C.","year":"2019","unstructured":"Helm , C. , and Taura , K . PerfMemPlus: A Tool for Automatic Discovery of Memory Performance Problems. In 34th International Conference, ISC High Performance ( 2019 ). Helm, C., and Taura, K. PerfMemPlus: A Tool for Automatic Discovery of Memory Performance Problems. In 34th International Conference, ISC High Performance (2019)."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2013.6"},{"key":"e_1_3_2_1_8_1","unstructured":"Intel Corporation. Disclosure of h\/w prefetcher control on some intel processors. https:\/\/software.intel.com\/en-us\/articles\/disclosure-of-hw-prefetcher-control-on-some-intel-processors.  Intel Corporation. Disclosure of h\/w prefetcher control on some intel processors. https:\/\/software.intel.com\/en-us\/articles\/disclosure-of-hw-prefetcher-control-on-some-intel-processors."},{"key":"e_1_3_2_1_9_1","unstructured":"Intel Corporation. Finding your memory access performance bottlenecks. https:\/\/software.intel.com\/en-us\/articles\/finding-your-memory-access-performance-bottlenecks.  Intel Corporation. Finding your memory access performance bottlenecks. https:\/\/software.intel.com\/en-us\/articles\/finding-your-memory-access-performance-bottlenecks."},{"volume-title":"Intel 64 and IA-32 Architectures Software Developer's Manual","author":"Intel Croporation","key":"e_1_3_2_1_10_1","unstructured":"Intel Croporation . Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3 . Intel Croporation. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3."},{"key":"e_1_3_2_1_11_1","unstructured":"Linux. Perf. https:\/\/perf.wiki.kernel.org\/index.php\/Main_Page.  Linux. Perf. https:\/\/perf.wiki.kernel.org\/index.php\/Main_Page."},{"key":"e_1_3_2_1_12_1","unstructured":"McCalpin John D. STREAM benchmark. http:\/\/www.cs.virginia.edu\/stream\/.  McCalpin John D. STREAM benchmark. http:\/\/www.cs.virginia.edu\/stream\/."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3030207.3030223"},{"key":"e_1_3_2_1_14_1","volume-title":"Collecting Performance Data with PAPI-C. Tools for High Performance Computing","author":"Terpstra D.","year":"2010","unstructured":"Terpstra , D. , Jagode , H. , You , H. , and Dongarra , J . Collecting Performance Data with PAPI-C. Tools for High Performance Computing ( 2010 ). Terpstra, D., Jagode, H., You, H., and Dongarra, J. Collecting Performance Data with PAPI-C. Tools for High Performance Computing (2010)."},{"key":"e_1_3_2_1_15_1","series-title":"Lecture Notes in Computer Science 6067 LNCS","volume-title":"Introducing a performance model for bandwidth-limited loop kernels","author":"Treibig J.","year":"2010","unstructured":"Treibig , J. , and Hager , G . Introducing a performance model for bandwidth-limited loop kernels . Lecture Notes in Computer Science 6067 LNCS ( 2010 ), 615--624. Treibig, J., and Hager, G. Introducing a performance model for bandwidth-limited loop kernels. Lecture Notes in Computer Science 6067 LNCS (2010), 615--624."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPPW.2010.38"},{"key":"e_1_3_2_1_17_1","first-page":"42","volume-title":"Proceedings of VPA 2014:  1st Workshop on Visual Performance Analysis","author":"Weyers E.","year":"2015","unstructured":"Weyers , E. , Terboven , C. , Schmidl , D. , Herber , J. , Kuhlen , T. W. , M\u00fcller , M. S. , and Hentschel , B . Visualization of Memory Access Behavior on Hierarchical NUMA Architectures . In Proceedings of VPA 2014: 1st Workshop on Visual Performance Analysis ( 2015 ), pp. 42 -- 49 . Weyers, E., Terboven, C., Schmidl, D., Herber, J., Kuhlen, T. W., M\u00fcller, M. S., and Hentschel, B. Visualization of Memory Access Behavior on Hierarchical NUMA Architectures. In Proceedings of VPA 2014: 1st Workshop on Visual Performance Analysis (2015), pp. 42--49."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1498765.1498785"},{"key":"e_1_3_2_1_19_1","volume-title":"DR-BW: Identifying Bandwidth Contention in NUMA Architectures with Supervised Learning. In IEEE International Parallel and Distributed Processing Symposium, IPDPS","author":"Xu H.","year":"2017","unstructured":"Xu , H. , Wen , S. , Gimenez , A. , Gamblin , T. , and Liu , X . DR-BW: Identifying Bandwidth Contention in NUMA Architectures with Supervised Learning. In IEEE International Parallel and Distributed Processing Symposium, IPDPS ( 2017 ). Xu, H., Wen, S., Gimenez, A., Gamblin, T., and Liu, X. DR-BW: Identifying Bandwidth Contention in NUMA Architectures with Supervised Learning. In IEEE International Parallel and Distributed Processing Symposium, IPDPS (2017)."},{"key":"e_1_3_2_1_20_1","first-page":"35","volume-title":"A. A Top-Down Method for Performance Analysis and Counters Architecture. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","author":"Yasin","year":"2014","unstructured":"Yasin , A. A Top-Down Method for Performance Analysis and Counters Architecture. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) ( 2014 ), pp. 35 -- 44 . Yasin, A. A Top-Down Method for Performance Analysis and Counters Architecture. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) (2014), pp. 35--44."}],"event":{"name":"HPCAsia2020: International Conference on High Performance Computing in Asia-Pacific Region","sponsor":["IPSJ","SIGHPC ACM Special Interest Group on High Performance Computing, Special Interest Group on High Performance Computing"],"location":"Fukuoka Japan","acronym":"HPCAsia2020"},"container-title":["Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3368474.3368476","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3368474.3368476","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:01:25Z","timestamp":1750197685000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3368474.3368476"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,1,15]]},"references-count":19,"alternative-id":["10.1145\/3368474.3368476","10.1145\/3368474"],"URL":"https:\/\/doi.org\/10.1145\/3368474.3368476","relation":{},"subject":[],"published":{"date-parts":[[2020,1,15]]},"assertion":[{"value":"2020-01-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}