{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,27]],"date-time":"2026-06-27T19:49:12Z","timestamp":1782589752063,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,1,15]],"date-time":"2020-01-15T00:00:00Z","timestamp":1579046400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,1,15]]},"DOI":"10.1145\/3368474.3368496","type":"proceedings-article","created":{"date-parts":[[2019,12,17]],"date-time":"2019-12-17T13:31:42Z","timestamp":1576589502000},"page":"207-216","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core"],"prefix":"10.1145","author":[{"given":"Susumu","family":"Mashimo","sequence":"first","affiliation":[{"name":"Kyushu University, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ryota","family":"Shioya","sequence":"additional","affiliation":[{"name":"The University of Tokyo, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Koji","family":"Inoue","sequence":"additional","affiliation":[{"name":"Kyushu University, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2020,1,15]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2629677"},{"key":"e_1_3_2_1_2_1","unstructured":"Intel Corporation. 2008. First the tick now the tock: next generation Intel microarchitecture (Nehalem).  Intel Corporation. 2008. First the tick now the tock: next generation Intel microarchitecture (Nehalem)."},{"key":"e_1_3_2_1_3_1","unstructured":"NVIDIA Corporation. 2011. Variable SMP - a multi-core CPUarchitecture for low power and high performance.  NVIDIA Corporation. 2011. Variable SMP - a multi-core CPUarchitecture for low power and high performance."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830812"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798281"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1755913.1755928"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253185"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_1_9_1","unstructured":"ARM Limited. 2013. big.LITTLE Technology: The Future of Mobile.  ARM Limited. 2013. big.LITTLE Technology: The Future of Mobile."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.37"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451143"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2005.1"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183532"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540746"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830791"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.35"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024407"},{"key":"e_1_3_2_1_20_1","volume-title":"SPEC CPU 2017","author":"Standard Performance Evaluation Corporation","year":"2019","unstructured":"Standard Performance Evaluation Corporation . 2019 . SPEC CPU 2017 . https:\/\/www.spec.org\/cpu2017\/. Standard Performance Evaluation Corporation. 2019. SPEC CPU 2017. https:\/\/www.spec.org\/cpu2017\/."},{"key":"e_1_3_2_1_21_1","volume-title":"45th International Symposium on Microarchitecture. 305--316","author":"Suleman M Aater","year":"2012","unstructured":"M Aater Suleman , Milad Hashemi , Chris Wilkerson , Yale N Patt , 2012 . Morphcore: An energy-efficient microarchitecture for high performance ilp and high throughput tlp . In 45th International Symposium on Microarchitecture. 305--316 . M Aater Suleman, Milad Hashemi, Chris Wilkerson, Yale N Patt, et al. 2012. Morphcore: An energy-efficient microarchitecture for high performance ilp and high throughput tlp. In 45th International Symposium on Microarchitecture. 305--316."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237019"}],"event":{"name":"HPCAsia2020: International Conference on High Performance Computing in Asia-Pacific Region","location":"Fukuoka Japan","acronym":"HPCAsia2020","sponsor":["IPSJ","SIGHPC ACM Special Interest Group on High Performance Computing, Special Interest Group on High Performance Computing"]},"container-title":["Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3368474.3368496","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3368474.3368496","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:01:26Z","timestamp":1750197686000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3368474.3368496"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,1,15]]},"references-count":20,"alternative-id":["10.1145\/3368474.3368496","10.1145\/3368474"],"URL":"https:\/\/doi.org\/10.1145\/3368474.3368496","relation":{},"subject":[],"published":{"date-parts":[[2020,1,15]]},"assertion":[{"value":"2020-01-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}