{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T16:00:30Z","timestamp":1774540830121,"version":"3.50.1"},"reference-count":64,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2019,12,26]],"date-time":"2019-12-26T00:00:00Z","timestamp":1577318400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"German Research Council (DFG) through the TraceSymm Project","award":["CA 1602\/4-1"],"award-info":[{"award-number":["CA 1602\/4-1"]}]},{"name":"Cluster of Excellence \u201cCenter for Advancing Electronics Dresden\u201d"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2019,12,31]]},"abstract":"<jats:p>\n            <jats:italic>Racetrack memories<\/jats:italic>\n            (RMs) have significantly evolved since their conception in 2008, making them a serious contender in the field of emerging memory technologies. Despite key technological advancements, the access latency and energy consumption of an RM-based system are still highly influenced by the number of\n            <jats:italic>shift<\/jats:italic>\n            operations. These operations are required to move bits to the right positions in the racetracks. This article presents data-placement techniques for RMs that maximize the likelihood that consecutive references access nearby memory locations at runtime, thereby minimizing the number of shifts. We present an\n            <jats:italic>integer linear programming<\/jats:italic>\n            (ILP) formulation for optimal data placement in RMs, and we revisit existing offset assignment heuristics, originally proposed for random-access memories. We introduce a novel heuristic tailored to a realistic RM and combine it with a genetic search to further improve the solution. We show a reduction in the number of shifts of up to 52.5%, outperforming the state of the art by up to 16.1%.\n          <\/jats:p>","DOI":"10.1145\/3372489","type":"journal-article","created":{"date-parts":[[2019,12,26]],"date-time":"2019-12-26T21:05:46Z","timestamp":1577394346000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":30,"title":["ShiftsReduce"],"prefix":"10.1145","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5130-9855","authenticated-orcid":false,"given":"Asif Ali","family":"Khan","sequence":"first","affiliation":[{"name":"Chair for Compiler Construction, Technische Universit\u00e4t Dresden, Dresden, Germany"}]},{"given":"Fazal","family":"Hameed","sequence":"additional","affiliation":[{"name":"Chair for Compiler Construction, Technische Universitat Dresden, Germany and Institute of Space Technology, Pakistan"}]},{"given":"Robin","family":"Bl\u00e4sing","sequence":"additional","affiliation":[{"name":"Max Planck Institute of Microstructure Physics, Halle (Saale), Germany"}]},{"given":"Stuart S. P.","family":"Parkin","sequence":"additional","affiliation":[{"name":"Max Planck Institute of Microstructure Physics, Halle (Saale), Germany"}]},{"given":"Jeronimo","family":"Castrillon","sequence":"additional","affiliation":[{"name":"Chair for Compiler Construction, Technische Universit\u00e4t Dresden, Germany"}]}],"member":"320","published-online":{"date-parts":[[2019,12,26]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2015.7324558"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the 13th International Workshop on Languages and Compilers for Parallel Computing-Revised Papers (LCPC\u201900)","author":"Atri Sunil"},{"key":"e_1_2_1_3_1","first-page":"2","article-title":"Optimizing stack frame accesses for processors with restricted addressing modes","volume":"22","author":"Bartley David H.","year":"1992","journal-title":"Softw. Pract. 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