{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:24:10Z","timestamp":1750220650555,"version":"3.41.0"},"reference-count":25,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2020,1,28]],"date-time":"2020-01-28T00:00:00Z","timestamp":1580169600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2020,3,31]]},"abstract":"<jats:p>High-level synthesis (HLS) has gained considerable traction over recent years, as it allows for faster development and verification of hardware accelerators than traditional RTL design. While HLS allows for most bugs to be caught during software verification, certain non-deterministic or data-dependent bugs still require debugging the actual hardware system during execution. Recent work has focused on techniques to allow designers to perform in-system debug of HLS circuits in the context of the original software code; however, like RTL debug, the user must still determine the root cause of a bug using small execution traces, with lengthy debug turns.<\/jats:p>\n          <jats:p>In this work, we demonstrate techniques aimed at reducing the time HLS designers spend performing in-system debug. Our approaches consist of performing data dependency analysis to guide the user in selecting which variables are observed by the debug instrumentation, as well as an associated debug overlay that allows for rapid reconfiguration of the debug logic, enabling rapid switching of variable observation between debug iterations. In addition, our overlay provides additional debug capability, such as selective function tracing and conditional buffer freeze points. We explore the area overhead of these different overlay features, showing a basic overlay with only a 1.7% increase in area overhead from the baseline debug instrumentation, while a deluxe variant offers 2\u00d7--7\u00d7 improvement in trace buffer memory utilization with conditional buffer freeze support.<\/jats:p>","DOI":"10.1145\/3372490","type":"journal-article","created":{"date-parts":[[2020,4,4]],"date-time":"2020-04-04T11:09:58Z","timestamp":1585998598000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays"],"prefix":"10.1145","volume":"13","author":[{"given":"Al-Shahna","family":"Jamal","sequence":"first","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eli","family":"Cahill","sequence":"additional","affiliation":[{"name":"Brigham Young University, BYU, Provo, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeffrey","family":"Goeders","sequence":"additional","affiliation":[{"name":"Brigham Young University, BYU, Provo, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven J. E.","family":"Wilton","sequence":"additional","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,1,28]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Altera. 2016. Altera Virtual JTAG (altera_virtual_jtag) IP Core User Guide. Retrieved from https:\/\/www.altera.com\/en_US\/pdfs\/literature\/ug\/ug_virtualjtag.pdf.  Altera. 2016. Altera Virtual JTAG (altera_virtual_jtag) IP Core User Guide. Retrieved from https:\/\/www.altera.com\/en_US\/pdfs\/literature\/ug\/ug_virtualjtag.pdf."},{"key":"e_1_2_1_2_1","unstructured":"Altera. 2016. SDK for OpenCL. Retrieved from https:\/\/www.altera.com\/products\/design-software\/embedded-software-developers\/opencl\/overview.html.  Altera. 2016. SDK for OpenCL. Retrieved from https:\/\/www.altera.com\/products\/design-software\/embedded-software-developers\/opencl\/overview.html."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056800"},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications.","author":"Calagar N.","key":"e_1_2_1_4_1"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898002"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2514740"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.80"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2015.7393127"},{"volume-title":"Proceedings of the International Conference on Computer Design. 251--258","year":"2015","author":"Fezzardi P.","key":"e_1_2_1_9_1"},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications. 1--9. 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S.","key":"e_1_2_1_17_1"},{"volume-title":"Proceedings of the International Symposium on Field-Programmable Gate Arrays. 5--8.","author":"Monson J. S.","key":"e_1_2_1_18_1"},{"key":"e_1_2_1_19_1","article-title":"A survey and evaluation of FPGA high-level synthesis tools","volume":"35","author":"Nane R.","year":"2016","journal-title":"IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2014.6983050"},{"key":"e_1_2_1_21_1","doi-asserted-by":"crossref","unstructured":"Hayden Kwok-Hay So and Cheng Liu. 2016. FPGA Overlays. Springer International Publishing Cham 285--305. DOI:https:\/\/doi.org\/10.1007\/978-3-319-26408-0_16  Hayden Kwok-Hay So and Cheng Liu. 2016. FPGA Overlays. Springer International Publishing Cham 285--305. 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Retrieved from http:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2016_2\/ug902-vivado-high-level-synthesis.pdf."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.38"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847313"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3372490","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3372490","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:02:22Z","timestamp":1750197742000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3372490"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,1,28]]},"references-count":25,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2020,3,31]]}},"alternative-id":["10.1145\/3372490"],"URL":"https:\/\/doi.org\/10.1145\/3372490","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2020,1,28]]},"assertion":[{"value":"2019-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-11-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-01-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}