{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,17]],"date-time":"2025-09-17T16:15:48Z","timestamp":1758125748577,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":63,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,3,9]],"date-time":"2020-03-09T00:00:00Z","timestamp":1583712000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Arm Limited"},{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council","doi-asserted-by":"publisher","award":["EP\/K026399\/1, EP\/P020011\/1 and EP\/M506485\/1"],"award-info":[{"award-number":["EP\/K026399\/1, EP\/P020011\/1 and EP\/M506485\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,3,9]]},"DOI":"10.1145\/3373376.3378463","type":"proceedings-article","created":{"date-parts":[[2020,3,13]],"date-time":"2020-03-13T22:37:01Z","timestamp":1584139021000},"page":"1277-1293","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["The Guardian Council"],"prefix":"10.1145","author":[{"given":"Sam","family":"Ainsworth","sequence":"first","affiliation":[{"name":"University of Cambridge, Cambridge, United Kingdom"}]},{"given":"Timothy M.","family":"Jones","sequence":"additional","affiliation":[{"name":"University of Cambridge, Cambridge, United Kingdom"}]}],"member":"320","published-online":{"date-parts":[[2020,3,13]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"http:\/\/xlab.tencent.com\/en\/2016\/11\/02\/return-flow-guard\/ 2016.  http:\/\/xlab.tencent.com\/en\/2016\/11\/02\/return-flow-guard\/ 2016."},{"key":"e_1_3_2_1_2_1","unstructured":"https:\/\/github.com\/google\/sanitizers\/wiki\/AddressSanitizerAlgorithm 2017.  https:\/\/github.com\/google\/sanitizers\/wiki\/AddressSanitizerAlgorithm 2017."},{"volume-title":"CCS","year":"2005","author":"Abadi M.","key":"e_1_3_2_1_3_1"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2018.00044"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2019.00032"},{"issue":"14","key":"e_1_3_2_1_6_1","article-title":"Smashing the stack for fun and profit","volume":"49","author":"One Aleph","year":"1998","journal-title":"Phrack Magazine"},{"volume-title":"http:\/\/www.anandtech.com\/show\/8542\/cortexm7-launches-embedded-iot-and-wearables\/2","year":"2014","key":"e_1_3_2_1_7_1"},{"volume-title":"http:\/\/www.anandtech.com\/show\/8718\/the-samsung-galaxy-note-4-exynos-review\/6","year":"2015","key":"e_1_3_2_1_8_1"},{"key":"e_1_3_2_1_9_1","unstructured":"ARM. http:\/\/www.arm.com\/products\/processors\/cortex-m\/cortex-m0plus.php.  ARM. http:\/\/www.arm.com\/products\/processors\/cortex-m\/cortex-m0plus.php."},{"key":"e_1_3_2_1_10_1","unstructured":"011)]etmmodelARM. Embedded trace macrocell architecture specification. http:\/\/infocenter.arm.com\/help\/index.jsp?topic=\/com.arm.doc.ihi0014q\/index.html 2011.  011)]etmmodelARM. Embedded trace macrocell architecture specification. http:\/\/infocenter.arm.com\/help\/index.jsp?topic=\/com.arm.doc.ihi0014q\/index.html 2011."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830801"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/2738600.2738611"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/178243.178446"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2442087.2442089"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0052259"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3071064.3071069"},{"volume-title":"Apr.","year":"2017","author":"Burow N.","key":"e_1_3_2_1_18_1"},{"volume-title":"S","author":"Burow N.","key":"e_1_3_2_1_19_1"},{"key":"e_1_3_2_1_20_1","unstructured":"P 2019.  P 2019."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2611765.2611766"},{"volume-title":"ISCA","year":"2008","author":"Chen S.","key":"e_1_3_2_1_22_1"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2010.20"},{"key":"e_1_3_2_1_24_1","article-title":"An analysis of secure processor architectures","author":"Chhabra S.","year":"2010","journal-title":"Transactions on Computational Science"},{"key":"e_1_3_2_1_25_1","unstructured":"]llvmcfiClang 10 documentation. Control flow integrity. https:\/\/clang.llvm.org\/docs\/ControlFlowIntegrity.html.  ]llvmcfiClang 10 documentation. Control flow integrity. https:\/\/clang.llvm.org\/docs\/ControlFlowIntegrity.html."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2810103.2813671"},{"volume-title":"ISCA","year":"2003","author":"Corliss M. L.","key":"e_1_3_2_1_27_1"},{"key":"e_1_3_2_1_28_1","volume-title":"DISCEX","volume":"2","author":"Cowan C.","year":"2000"},{"volume-title":"ISCA","year":"2013","author":"Demme J.","key":"e_1_3_2_1_29_1"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.17"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3029806.3029812"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1655077.1655083"},{"volume-title":"SSYM","year":"2001","author":"Frantzen M.","key":"e_1_3_2_1_33_1"},{"volume-title":"AES","year":"2004","author":"Giraud C.","key":"e_1_3_2_1_34_1"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3065913.3065915"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844457"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783740"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-26362-5_1"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2014.2332177"},{"volume-title":"ISCA","year":"2014","author":"Kim Y.","key":"e_1_3_2_1_40_1"},{"volume-title":"Jan.","year":"2018","author":"Kocher P.","key":"e_1_3_2_1_41_1"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.5555\/646761.706156"},{"key":"e_1_3_2_1_43_1","unstructured":"D. Lea. A memory allocator. http:\/\/gee.cs.oswego.edu\/dl\/html\/malloc.html.  D. Lea. A memory allocator. http:\/\/gee.cs.oswego.edu\/dl\/html\/malloc.html."},{"volume-title":"Jan.","year":"2018","author":"Lipp M.","key":"e_1_3_2_1_44_1"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056071"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/503272.503286"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2768566.2768575"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056070"},{"volume-title":"BSDCan","year":"2005","author":"Percival C.","key":"e_1_3_2_1_49_1"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2014.17"},{"volume-title":"Bypassing control flow guard in windows 10. https:\/\/improsec.com\/blog\/bypassing-control-flow-guard-in-windows-10","year":"2017","author":"Schenk M.","key":"e_1_3_2_1_51_1"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/353323.353382"},{"volume-title":"USENIX ATC","year":"2012","author":"Serebryany K.","key":"e_1_3_2_1_53_1"},{"volume-title":"CCS","year":"2007","author":"Shacham H.","key":"e_1_3_2_1_54_1"},{"issue":"2","key":"e_1_3_2_1_55_1","article-title":"Heapmon: A helper-thread approach to programmable, automatic, and low-overhead memory bug detection","volume":"50","author":"Shetty R.","year":"2006","journal-title":"IBM J. Res. Dev."},{"key":"e_1_3_2_1_56_1","unstructured":"A. L. Shimpi. ARM's Cortex M: Even smaller and lower power cpu cores. http:\/\/www.anandtech.com\/show\/8400\/arms-cortex-m-even-smaller-and-lower-power-cpu-cores 2014.  A. L. Shimpi. ARM's Cortex M: Even smaller and lower power cpu cores. http:\/\/www.anandtech.com\/show\/8400\/arms-cortex-m-even-smaller-and-lower-power-cpu-cores 2014."},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2013.13"},{"volume-title":"https:\/\/documents.trendmicro.com\/assets\/wp\/exploring-control-flow-guard-in-windows10.pdf","year":"2015","author":"Tang J.","key":"e_1_3_2_1_58_1"},{"key":"e_1_3_2_1_59_1","unstructured":"]contextswitchTsuna's blog. How long does it take to make a context switch? https:\/\/blog.tsunanet.net\/2010\/11\/how-long-does-it-take-to-make-context.html.  ]contextswitchTsuna's blog. How long does it take to make a context switch? https:\/\/blog.tsunanet.net\/2010\/11\/how-long-does-it-take-to-make-context.html."},{"key":"e_1_3_2_1_60_1","first-page":"2017","article-title":"Diasys: Improving soc insight through on-chip diagnosis","volume":"75","author":"Wagner P.","journal-title":"Journal of Systems Architecture"},{"volume-title":"USENIX Security","year":"2012","author":"Xu R.","key":"e_1_3_2_1_61_1"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757414"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903267"}],"event":{"name":"ASPLOS '20: Architectural Support for Programming Languages and Operating Systems","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Lausanne Switzerland","acronym":"ASPLOS '20"},"container-title":["Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3373376.3378463","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3373376.3378463","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:32:59Z","timestamp":1750199579000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3373376.3378463"}},"subtitle":["Parallel Programmable Hardware Security"],"short-title":[],"issued":{"date-parts":[[2020,3,9]]},"references-count":63,"alternative-id":["10.1145\/3373376.3378463","10.1145\/3373376"],"URL":"https:\/\/doi.org\/10.1145\/3373376.3378463","relation":{},"subject":[],"published":{"date-parts":[[2020,3,9]]},"assertion":[{"value":"2020-03-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}