{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,25]],"date-time":"2026-03-25T08:43:43Z","timestamp":1774428223288,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":71,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,3,9]],"date-time":"2020-03-09T00:00:00Z","timestamp":1583712000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1649432"],"award-info":[{"award-number":["1649432"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,3,9]]},"DOI":"10.1145\/3373376.3378493","type":"proceedings-article","created":{"date-parts":[[2020,3,13]],"date-time":"2020-03-13T22:37:01Z","timestamp":1584139021000},"page":"1093-1108","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":51,"title":["Elastic Cuckoo Page Tables"],"prefix":"10.1145","author":[{"given":"Dimitrios","family":"Skarlatos","sequence":"first","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL, USA"}]},{"given":"Apostolos","family":"Kokolis","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL, USA"}]},{"given":"Tianyin","family":"Xu","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL, USA"}]},{"given":"Josep","family":"Torrellas","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL, USA"}]}],"member":"320","published-online":{"date-parts":[[2020,3,13]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/2337159.2337214"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080209"},{"key":"e_1_3_2_1_3_1","volume-title":"BioBench: A Benchmark Suite of Bioinformatics Applications. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'05)","author":"Albayraktaroglu Kursad","year":"2005","unstructured":"Kursad Albayraktaroglu , Aamer Jaleel , Xue Wu , Manoj Franklin , Bruce Jacob , Chau-Wen Tseng , and Donald Yeung . 2005 . BioBench: A Benchmark Suite of Bioinformatics Applications. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'05) . Kursad Albayraktaroglu, Aamer Jaleel, Xue Wu, Manoj Franklin, Bruce Jacob, Chau-Wen Tseng, and Donald Yeung. 2005. BioBench: A Benchmark Suite of Bioinformatics Applications. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'05) ."},{"key":"e_1_3_2_1_4_1","unstructured":"AMD. 2019. Architecture Programmer's Manual (Volume 2) . https:\/\/www.amd.com\/system\/files\/TechDocs\/24593.pdf .  AMD. 2019. Architecture Programmer's Manual (Volume 2) . https:\/\/www.amd.com\/system\/files\/TechDocs\/24593.pdf ."},{"key":"e_1_3_2_1_5_1","volume-title":"The Hash Function BLAKE","author":"Aumasson Jean-Philippe","unstructured":"Jean-Philippe Aumasson , Willi Meier , Raphael Phan , and Luca Henzen . 2014. The Hash Function BLAKE . Springer . Jean-Philippe Aumasson, Willi Meier, Raphael Phan, and Luca Henzen. 2014. The Hash Function BLAKE. Springer."},{"key":"e_1_3_2_1_6_1","volume-title":"Samba: A Detailed Memory Management Unit (MMU) for the SST Simulation Framework. Technical Report SAND2017-0002","author":"Awad A.","unstructured":"A. Awad , S. D. Hammond , G. R. Voskuilen , and R. J. Hoekstra . 2017 . Samba: A Detailed Memory Management Unit (MMU) for the SST Simulation Framework. Technical Report SAND2017-0002 . Sandia National Laboratories. A. Awad, S. D. Hammond, G. R. Voskuilen, and R. J. Hoekstra. 2017. Samba: A Detailed Memory Management Unit (MMU) for the SST Simulation Framework. Technical Report SAND2017-0002. Sandia National Laboratories."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3085572"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815970"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000101"},{"key":"e_1_3_2_1_10_1","volume-title":"Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA'13)","author":"Basu Arkaprava","unstructured":"Arkaprava Basu , Jayneel Gandhi , Jichuan Chang , Mark D. Hill , and Michael M. Swift . 2013. Efficient Virtual Memory for Big Memory Servers . In Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA'13) . Arkaprava Basu, Jayneel Gandhi, Jichuan Chang, Mark D. Hill, and Michael M. Swift. 2013. Efficient Virtual Memory for Big Memory Servers . In Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA'13) ."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1346281.1346286"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540741"},{"key":"e_1_3_2_1_13_1","volume-title":"Translation-Triggered Prefetching. In Proceedings of the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'17)","author":"Bhattacharjee Abhishek","year":"2017","unstructured":"Abhishek Bhattacharjee . 2017 . Translation-Triggered Prefetching. In Proceedings of the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'17) . Abhishek Bhattacharjee. 2017. Translation-Triggered Prefetching. In Proceedings of the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'17) ."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/2014698.2014896"},{"key":"e_1_3_2_1_15_1","volume-title":"Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XV) .","author":"Bhattacharjee Abhishek","year":"2010","unstructured":"Abhishek Bhattacharjee and Margaret Martonosi . 2010 . Inter-Core Cooperative TLB Prefetchers for Chip Multiprocessors . In Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XV) . Abhishek Bhattacharjee and Margaret Martonosi. 2010. Inter-Core Cooperative TLB Prefetchers for Chip Multiprocessors. In Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XV) ."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2925426.2926293"},{"key":"e_1_3_2_1_18_1","volume-title":"Proceedings of the 19th Annual International Symposium on Computer Architecture (ISCA'92)","author":"Chen J. Bradley","unstructured":"J. Bradley Chen , Anita Borg , and Norman P. Jouppi . 1992. A Simulation Based Study of TLB Performance . In Proceedings of the 19th Annual International Symposium on Computer Architecture (ISCA'92) . J. Bradley Chen, Anita Borg, and Norman P. Jouppi. 1992. A Simulation Based Study of TLB Performance. In Proceedings of the 19th Annual International Symposium on Computer Architecture (ISCA'92) ."},{"key":"e_1_3_2_1_19_1","unstructured":"Jonathan Corbet. 2005. Four-level page tables . https:\/\/lwn.net\/Articles\/117749\/.  Jonathan Corbet. 2005. Four-level page tables . https:\/\/lwn.net\/Articles\/117749\/."},{"key":"e_1_3_2_1_20_1","unstructured":"Jonathan Corbet. 2017. Five-level page tables . https:\/\/lwn.net\/Articles\/717293\/.  Jonathan Corbet. 2017. Five-level page tables . https:\/\/lwn.net\/Articles\/717293\/."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037704"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/296806.296833"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00224-004-1195-x"},{"key":"e_1_3_2_1_25_1","volume-title":"Proceedings of the 47th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-47)","author":"Gandhi Jayneel","unstructured":"Jayneel Gandhi , Arkaprava Basu , Mark D. Hill , and Michael M. Swift . 2014. Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks . In Proceedings of the 47th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-47) . Jayneel Gandhi, Arkaprava Basu, Mark D. Hill, and Michael M. Swift. 2014. Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks. In Proceedings of the 47th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-47) ."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/2643634.2643659"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-24322-6_24"},{"key":"e_1_3_2_1_28_1","volume-title":"Proceedings of the 2005 USENIX Annual Technical Conference (USENIX ATC'05) .","author":"Gray Charles","year":"2005","unstructured":"Charles Gray , Matthew Chapman , Peter Chubb , David Mosberger-Tang , and Gernot Heiser . 2005 . Itanium -- A System Implementor's Tale . In Proceedings of the 2005 USENIX Annual Technical Conference (USENIX ATC'05) . Charles Gray, Matthew Chapman, Peter Chubb, David Mosberger-Tang, and Gernot Heiser. 2005. Itanium -- A System Implementor's Tale. In Proceedings of the 2005 USENIX Annual Technical Conference (USENIX ATC'05) ."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2731186.2731187"},{"key":"e_1_3_2_1_30_1","volume-title":"Platform Storage Performance With 3D XPoint Technology . Proc","author":"Hady Frank T.","year":"2017","unstructured":"Frank T. Hady , Annie P. Foong , Bryan Veal , and Dan Williams . 2017. Platform Storage Performance With 3D XPoint Technology . Proc . IEEE , Vol . 105, 9 ( 2017 ). Frank T. Hady, Annie P. Foong, Bryan Veal, and Dan Williams. 2017. Platform Storage Performance With 3D XPoint Technology . Proc. IEEE , Vol. 105, 9 (2017)."},{"key":"e_1_3_2_1_31_1","volume-title":"Proceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'18)","author":"Haria Swapnil","unstructured":"Swapnil Haria , Mark D. Hill , and Michael M. Swift . 2018. Devirtualizing Memory in Heterogeneous Systems . In Proceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'18) . Swapnil Haria, Mark D. Hill, and Michael M. Swift. 2018. Devirtualizing Memory in Heterogeneous Systems . In Proceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'18) ."},{"key":"e_1_3_2_1_32_1","volume-title":"SPEC CPU2006 Benchmark Descriptions . ACM SIGARCH Computer Architecture News","volume":"34","author":"Henning John L.","year":"2006","unstructured":"John L. Henning . 2006 . SPEC CPU2006 Benchmark Descriptions . ACM SIGARCH Computer Architecture News , Vol. 34 , 4 (Sept. 2006), 1--17. John L. Henning. 2006. SPEC CPU2006 Benchmark Descriptions . ACM SIGARCH Computer Architecture News , Vol. 34, 4 (Sept. 2006), 1--17."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165128"},{"key":"e_1_3_2_1_34_1","unstructured":"IBM. 2005. PowerPC$^\u00ae$ Microprocessor Family: The Programming Environments Manual for 32 and 64-bit Microprocessors . https:\/\/wiki.alcf.anl.gov\/images\/f\/fb\/PowerPC_-_Assembly_-_IBM_Programming_Environment_2.3.pdf .  IBM. 2005. PowerPC$^\u00ae$ Microprocessor Family: The Programming Environments Manual for 32 and 64-bit Microprocessors . https:\/\/wiki.alcf.anl.gov\/images\/f\/fb\/PowerPC_-_Assembly_-_IBM_Programming_Environment_2.3.pdf ."},{"key":"e_1_3_2_1_35_1","unstructured":"Intel$^\u00ae$. 2010. Itanium$^\u00ae$ Architecture Software Developer's Manual (Volume 2) . https:\/\/www.intel.com\/content\/www\/us\/en\/products\/docs\/processors\/itanium\/itanium-architecture-vol-1--2--3--4-reference-set-manual.html .  Intel$^\u00ae$. 2010. Itanium$^\u00ae$ Architecture Software Developer's Manual (Volume 2) . https:\/\/www.intel.com\/content\/www\/us\/en\/products\/docs\/processors\/itanium\/itanium-architecture-vol-1--2--3--4-reference-set-manual.html ."},{"key":"e_1_3_2_1_36_1","unstructured":"Intel. 2015. 5-Level Paging and 5-Level EPT (White Paper) . https:\/\/software.intel.com\/sites\/default\/files\/managed\/2b\/80\/5-level_paging_white_paper.pdf .  Intel. 2015. 5-Level Paging and 5-Level EPT (White Paper) . https:\/\/software.intel.com\/sites\/default\/files\/managed\/2b\/80\/5-level_paging_white_paper.pdf ."},{"key":"e_1_3_2_1_37_1","unstructured":"Intel. 2018. Sunny Cove Microarchitecture . https:\/\/en.wikichip.org\/wiki\/intel\/microarchitectures\/sunny_cove .  Intel. 2018. Sunny Cove Microarchitecture . https:\/\/en.wikichip.org\/wiki\/intel\/microarchitectures\/sunny_cove ."},{"key":"e_1_3_2_1_38_1","unstructured":"Intel$^\u00ae$. 2019. 64 and IA-32 Architectures Software Developer's Manual .  Intel$^\u00ae$. 2019. 64 and IA-32 Architectures Software Developer's Manual ."},{"key":"e_1_3_2_1_39_1","volume-title":"Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VIII) .","author":"Bruce","unstructured":"Bruce L. Jacob and Trevor N. Mudge. 1998. A Look at Several Memory Management Units, TLB-refill Mechanisms, and Page Table Organizations . In Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VIII) . Bruce L. Jacob and Trevor N. Mudge. 1998. A Look at Several Memory Management Units, TLB-refill Mechanisms, and Page Table Organizations. In Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VIII) ."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2018.2846959"},{"key":"e_1_3_2_1_41_1","volume-title":"Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA'02)","author":"Gokul","unstructured":"Gokul B. Kandiraju and Anand Sivasubramaniam. 2002. Going the Distance for TLB Prefetching: An Application-driven Study . In Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA'02) . Gokul B. Kandiraju and Anand Sivasubramaniam. 2002. Going the Distance for TLB Prefetching: An Application-driven Study. In Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA'02) ."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2749471"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.5555\/3026877.3026931"},{"key":"e_1_3_2_1_44_1","unstructured":"Linux Kernel. 2019. Page Table Types. https:\/\/git.kernel.org\/pub\/scm\/linux\/kernel\/git\/stable\/linux.git\/tree\/arch\/x86\/include\/asm\/pgtable_types.h?h=v4.19.1 .  Linux Kernel. 2019. Page Table Types. https:\/\/git.kernel.org\/pub\/scm\/linux\/kernel\/git\/stable\/linux.git\/tree\/arch\/x86\/include\/asm\/pgtable_types.h?h=v4.19.1 ."},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1188455.1188677"},{"key":"e_1_3_2_1_46_1","volume-title":"Simics: A Full System Simulation Platform","author":"Magnusson Peter S.","year":"2002","unstructured":"Peter S. Magnusson , Magnus Christensson , Jesper Eskilson , Daniel Forsgren , Gustav H\u00e5llberg , Johan H\u00f6gberg , Fredrik Larsson , Andreas Moestedt , and Bengt Werner . 2002 . Simics: A Full System Simulation Platform . IEEE Computer ( 2002). Peter S. Magnusson, Magnus Christensson, Jesper Eskilson, Daniel Forsgren, Gustav H\u00e5llberg, Johan H\u00f6gberg, Fredrik Larsson, Andreas Moestedt, and Bengt Werner. 2002. Simics: A Full System Simulation Platform . IEEE Computer (2002)."},{"key":"e_1_3_2_1_47_1","volume-title":"Proceedings of the 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-50)","author":"Marathe Yashwant","unstructured":"Yashwant Marathe , Nagendra Gulur , Jee Ho Ryoo , Shuang Song , and Lizy K. John . 2017. CSALT: Context Switch Aware Large TLB . In Proceedings of the 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-50) . Yashwant Marathe, Nagendra Gulur, Jee Ho Ryoo, Shuang Song, and Lizy K. John. 2017. CSALT: Context Switch Aware Large TLB. In Proceedings of the 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-50) ."},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/2807591.2807626"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1060289.1060299"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jalgor.2003.12.002"},{"key":"e_1_3_2_1_51_1","volume-title":"Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'19)","author":"Panwar Ashish","unstructured":"Ashish Panwar , Sorav Bansal , and K. Gopinath . 2019. HawkEye: Efficient Fine-grained OS Support for Huge Pages . In Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'19) . Ashish Panwar, Sorav Bansal, and K. Gopinath. 2019. HawkEye: Efficient Fine-grained OS Support for Huge Pages. In Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'19) ."},{"key":"e_1_3_2_1_52_1","volume-title":"Proceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'18)","author":"Panwar Ashish","unstructured":"Ashish Panwar , Aravinda Prasad , and K. Gopinath . 2018. Making Huge Pages Actually Useful . In Proceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'18) . Ashish Panwar, Aravinda Prasad, and K. Gopinath. 2018. Making Huge Pages Actually Useful. In Proceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'18) ."},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056034"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080217"},{"key":"e_1_3_2_1_55_1","volume-title":"Proceedings of the 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA'14)","author":"Pham Binh","unstructured":"Binh Pham , Abhishek Bhattacharjee , Yasuko Eckert , and Gabriel H. Loh . 2014. Increasing TLB Reach by Exploiting Clustering in Page Translations . In Proceedings of the 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA'14) . Binh Pham, Abhishek Bhattacharjee, Yasuko Eckert, and Gabriel H. Loh. 2014. Increasing TLB Reach by Exploiting Clustering in Page Translations. In Proceedings of the 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA'14) ."},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.32"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830773"},{"key":"e_1_3_2_1_58_1","volume-title":"Phase Change Memory: From Devices to Systems","author":"Qureshi Moinuddin K.","unstructured":"Moinuddin K. Qureshi , Sudhanva Gurumurthi , and Bipin Rajendran . 2011. Phase Change Memory: From Devices to Systems 1 st ed.). Morgan & Claypool Publishers . Moinuddin K. Qureshi, Sudhanva Gurumurthi, and Bipin Rajendran. 2011. Phase Change Memory: From Devices to Systems 1st ed.). Morgan & Claypool Publishers.","edition":"1"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/1188455.1188618"},{"key":"e_1_3_2_1_60_1","volume-title":"Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA'95)","author":"Romer Theodore H.","unstructured":"Theodore H. Romer , Wayne H. Ohlrich , Anna R. Karlin , and Brian N. Bershad . 1995. Reducing TLB and Memory Overhead Using Online Superpage Promotion . In Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA'95) . Theodore H. Romer, Wayne H. Ohlrich, Anna R. Karlin, and Brian N. Bershad. 1995. Reducing TLB and Memory Overhead Using Online Superpage Promotion. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA'95) ."},{"key":"e_1_3_2_1_61_1","volume-title":"DRAMSim2: A Cycle Accurate Memory System Simulator","author":"Rosenfeld Paul","year":"2011","unstructured":"Paul Rosenfeld , Elliott Cooper-Balis , and Bruce Jacob . 2011. DRAMSim2: A Cycle Accurate Memory System Simulator . IEEE Computer Architecture Letters ( 2011 ). Paul Rosenfeld, Elliott Cooper-Balis, and Bruce Jacob. 2011. DRAMSim2: A Cycle Accurate Memory System Simulator . IEEE Computer Architecture Letters (2011)."},{"key":"e_1_3_2_1_62_1","volume-title":"Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA'17)","author":"Ryoo Jee Ho","unstructured":"Jee Ho Ryoo , Nagendra Gulur , Shuang Song , and Lizy K. John . 2017. Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB . In Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA'17) . Jee Ho Ryoo, Nagendra Gulur, Shuang Song, and Lizy K. John. 2017. Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB. In Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA'17) ."},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339666"},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.26"},{"key":"e_1_3_2_1_65_1","unstructured":"Synopsys. 2019. Design Compiler. https:\/\/www.synopsys.com .  Synopsys. 2019. Design Compiler. https:\/\/www.synopsys.com ."},{"key":"e_1_3_2_1_66_1","unstructured":"SysBench. 2019. A modular cross-platform and multi-threaded benchmark tool. http:\/\/manpages.ubuntu.com\/manpages\/trusty\/man1\/sysbench.1.html .  SysBench. 2019. A modular cross-platform and multi-threaded benchmark tool. http:\/\/manpages.ubuntu.com\/manpages\/trusty\/man1\/sysbench.1.html ."},{"key":"e_1_3_2_1_67_1","volume-title":"Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VI) .","author":"Talluri Madhusudhan","unstructured":"Madhusudhan Talluri and Mark D. Hill . 1994. Surpassing the TLB Performance of Superpages with Less Operating System Support . In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VI) . Madhusudhan Talluri and Mark D. Hill. 1994. Surpassing the TLB Performance of Superpages with Less Operating System Support. In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VI) ."},{"key":"e_1_3_2_1_68_1","volume-title":"Proceedings of the 15th ACM Symposium on Operating Systems Principles (SOSP'95)","author":"Talluri Madhusudhan","unstructured":"Madhusudhan Talluri , Mark D. Hill , and Yousef A. Khalidi . 1995. A New Page Table for 64-bit Address Spaces . In Proceedings of the 15th ACM Symposium on Operating Systems Principles (SOSP'95) . Madhusudhan Talluri, Mark D. Hill, and Yousef A. Khalidi. 1995. A New Page Table for 64-bit Address Spaces. In Proceedings of the 15th ACM Symposium on Operating Systems Principles (SOSP'95) ."},{"key":"e_1_3_2_1_69_1","volume-title":"Tradeoffs in Supporting Two Page Sizes. In 19th International Symposium on Computer Architecture (ISCA'92)","author":"Talluri Madhusudhan","unstructured":"Madhusudhan Talluri , Shing Kong , Mark D. Hill , and David A. Patterson . 1992 . Tradeoffs in Supporting Two Page Sizes. In 19th International Symposium on Computer Architecture (ISCA'92) . Madhusudhan Talluri, Shing Kong, Mark D. Hill, and David A. Patterson. 1992. Tradeoffs in Supporting Two Page Sizes. In 19th International Symposium on Computer Architecture (ISCA'92) ."},{"key":"e_1_3_2_1_70_1","unstructured":"The Linux Kernel Archives. 2019. Transparent Hugepage Support. https:\/\/www.kernel.org\/doc\/Documentation\/vm\/transhuge.txt .  The Linux Kernel Archives. 2019. Transparent Hugepage Support. https:\/\/www.kernel.org\/doc\/Documentation\/vm\/transhuge.txt ."},{"key":"e_1_3_2_1_71_1","volume-title":"PHYSOR 2014 - The Role of Reactor Physics toward a Sustainable Future .","author":"Tramm John R","year":"2014","unstructured":"John R Tramm , Andrew R Siegel , Tanzima Islam , and Martin Schulz . 2014 . XSBench - The Development and Verification of a Performance Abstraction for Monte Carlo Reactor Analysis . In PHYSOR 2014 - The Role of Reactor Physics toward a Sustainable Future . John R Tramm, Andrew R Siegel, Tanzima Islam, and Martin Schulz. 2014. XSBench - The Development and Verification of a Performance Abstraction for Monte Carlo Reactor Analysis. In PHYSOR 2014 - The Role of Reactor Physics toward a Sustainable Future ."},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322223"},{"key":"e_1_3_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.1145\/2896377.2901456"}],"event":{"name":"ASPLOS '20: Architectural Support for Programming Languages and Operating Systems","location":"Lausanne Switzerland","acronym":"ASPLOS '20","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3373376.3378493","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3373376.3378493","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3373376.3378493","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:32:59Z","timestamp":1750199579000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3373376.3378493"}},"subtitle":["Rethinking Virtual Memory Translation for Parallelism"],"short-title":[],"issued":{"date-parts":[[2020,3,9]]},"references-count":71,"alternative-id":["10.1145\/3373376.3378493","10.1145\/3373376"],"URL":"https:\/\/doi.org\/10.1145\/3373376.3378493","relation":{},"subject":[],"published":{"date-parts":[[2020,3,9]]},"assertion":[{"value":"2020-03-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}