{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,3]],"date-time":"2026-01-03T14:46:50Z","timestamp":1767451610938,"version":"3.41.0"},"reference-count":49,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2020,3,4]],"date-time":"2020-03-04T00:00:00Z","timestamp":1583280000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2020,3,31]]},"abstract":"<jats:p>This work studies hardware-specific optimization opportunities currently unexploited by high-level synthesis compilers. Some of these optimizations are specializations of floating-point operations that respect the usual semantics of the input program without changing the numerical result. Some other optimizations, locally triggered by the programmer thanks to a pragma, assume a different semantics, where floating-point code is interpreted as the specification of computation with real numbers. The compiler is then in charge to ensure an application-level accuracy constraint expressed in the pragma and has the freedom to use non-standard arithmetic hardware when more efficient. These two classes of optimizations are prototyped in the GeCoS source-to-source compiler and evaluated on the Polybench and EEMBC benchmark suites. Latency is reduced by up to 93%, and resource usage is reduced by up to 58%.<\/jats:p>","DOI":"10.1145\/3377403","type":"journal-article","created":{"date-parts":[[2020,3,4]],"date-time":"2020-03-04T12:50:12Z","timestamp":1583326212000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Application-Specific Arithmetic in High-Level Synthesis Tools"],"prefix":"10.1145","volume":"17","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9455-1265","authenticated-orcid":false,"given":"Yohann","family":"Uguen","sequence":"first","affiliation":[{"name":"Univ. Lyon, INSA Lyon, Inria, CITI, Villeurbanne, France"}]},{"given":"Florent De","family":"Dinechin","sequence":"additional","affiliation":[{"name":"Univ. Lyon, INSA Lyon, Inria, CITI, Villeurbanne, France"}]},{"given":"Victor","family":"Lezaud","sequence":"additional","affiliation":[{"name":"Univ. Lyon, INSA Lyon, Inria, CITI, Villeurbanne, France"}]},{"given":"Steven","family":"Derrien","sequence":"additional","affiliation":[{"name":"Univ. Rennes 1, IRISA, France"}]}],"member":"320","published-online":{"date-parts":[[2020,3,4]]},"reference":[{"volume-title":"IEEE Standard for Binary Floating-Point Arithmetic. Standard 754-1985","author":"IEEE.","key":"e_1_2_1_1_1","unstructured":"IEEE. (n.d.). IEEE Standard for Binary Floating-Point Arithmetic. Standard 754-1985 . IEEE , Los Alamitos, CA . IEEE. (n.d.). IEEE Standard for Binary Floating-Point Arithmetic. Standard 754-1985. IEEE, Los Alamitos, CA."},{"key":"e_1_2_1_2_1","unstructured":"Intel. 2019. Intel High Level Synthesis Compiler: Best Practices Guide. Intel.  Intel. 2019. Intel High Level Synthesis Compiler: Best Practices Guide. Intel."},{"key":"e_1_2_1_3_1","unstructured":"Xilinx. 2019. Vivado Design Suite User Guide: High-Level Synthesis. Xilinx.  Xilinx. 2019. Vivado Design Suite User Guide: High-Level Synthesis. Xilinx."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375200"},{"key":"e_1_2_1_5_1","unstructured":"Randy Allen and Ken Kennedy. 2002. Optimizing Compilers for Modern Architectures. Morgan Kaufmann.  Randy Allen and Ken Kennedy. 2002. Optimizing Compilers for Modern Architectures. Morgan Kaufmann."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2008.4580184"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311288"},{"key":"e_1_2_1_8_1","volume-title":"Fast integer multipliers fit in FPGAs (EDN 1993 design idea winner). EDN Magazine 10 (May","author":"Chapman Ken","year":"1993","unstructured":"Ken Chapman . 1993. Fast integer multipliers fit in FPGAs (EDN 1993 design idea winner). EDN Magazine 10 (May 1993 ). Ken Chapman. 1993. Fast integer multipliers fit in FPGAs (EDN 1993 design idea winner). EDN Magazine 10 (May 1993)."},{"volume-title":"FPGAs for Software Programmers","author":"Cong Jason","key":"e_1_2_1_9_1","unstructured":"Jason Cong , Muhuan Huang , Peichen Pan , Yuxin Wang , and Peng Zhang . 2016. Source-to-source optimization for HLS . In FPGAs for Software Programmers . Springer , 137--163. Jason Cong, Muhuan Huang, Peichen Pan, Yuxin Wang, and Peng Zhang. 2016. Source-to-source optimization for HLS. In FPGAs for Software Programmers. Springer, 137--163."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2177706"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2019.00037"},{"volume-title":"High-Performance Computing Using FPGAs","author":"de Dinechin Florent","key":"e_1_2_1_12_1","unstructured":"Florent de Dinechin and Bogdan Pasca . 2013. Reconfigurable arithmetic for high performance computing . In High-Performance Computing Using FPGAs . Springer , 631--664. Florent de Dinechin and Bogdan Pasca. 2013. Reconfigurable arithmetic for high performance computing. In High-Performance Computing Using FPGAs. Springer, 631--664."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2008.4762363"},{"key":"e_1_2_1_14_1","volume-title":"IEE Proceedings\u2014Circuits, Devices and Systems 141","author":"Andrew","year":"1994","unstructured":"Andrew G. Dempster and Malcolm D. Macleod. 1994. Constant integer multiplication using minimum adders . IEE Proceedings\u2014Circuits, Devices and Systems 141 , 5 ( 1994 ), 407--413. Andrew G. Dempster and Malcolm D. Macleod. 1994. Constant integer multiplication using minimum adders. IEE Proceedings\u2014Circuits, Devices and Systems 141, 5 (1994), 407--413."},{"key":"e_1_2_1_15_1","first-page":"904","article-title":"Floating point multiplier\/accumulator with reduced latency and method thereof","volume":"6","author":"Dibrino Michael","year":"2005","unstructured":"Michael Dibrino . 2005 . Floating point multiplier\/accumulator with reduced latency and method thereof . US Patent 6 , 904 ,446. Michael Dibrino. 2005. Floating point multiplier\/accumulator with reduced latency and method thereof. US Patent 6,904,446.","journal-title":"US Patent"},{"key":"e_1_2_1_16_1","volume-title":"Proceedings of the International Workshop on Polyhedral Compilation Techniques.","author":"Doerfert Johannes","year":"2015","unstructured":"Johannes Doerfert , Kevin Streit , Sebastian Hack , and Zino Benaissa . 2015 . Polly\u2019s polyhedral scheduling in the presence of reductions . In Proceedings of the International Workshop on Polyhedral Compilation Techniques. Johannes Doerfert, Kevin Streit, Sebastian Hack, and Zino Benaissa. 2015. Polly\u2019s polyhedral scheduling in the presence of reductions. In Proceedings of the International Workshop on Polyhedral Compilation Techniques."},{"key":"e_1_2_1_17_1","volume-title":"Retrieved","author":"Embedded Microprocessor Benchmark Consortium EEMBC","year":"2013","unstructured":"EEMBC , the Embedded Microprocessor Benchmark Consortium . 2013 . Introduction to the EEMBC FPMarkTM FPMark Floating-Point Benchmark Suite . Retrieved January 29, 2020 from http:\/\/www.eembc.org\/fpmark. EEMBC, the Embedded Microprocessor Benchmark Consortium. 2013. Introduction to the EEMBC FPMarkTM FPMark Floating-Point Benchmark Suite. Retrieved January 29, 2020 from http:\/\/www.eembc.org\/fpmark."},{"key":"e_1_2_1_18_1","first-page":"730","article-title":"System and method for a floating point unit with feedback prior to normalization and rounding","volume":"7","author":"Fleischer Bruce M.","year":"2010","unstructured":"Bruce M. Fleischer , Juergen Haess , Michael Kroener , Martin S. Schmookler , Eric M. Schwarz , and Son Dao-Trong . 2010 . System and method for a floating point unit with feedback prior to normalization and rounding . US Patent 7 , 730 ,117. Bruce M. Fleischer, Juergen Haess, Michael Kroener, Martin S. Schmookler, Eric M. Schwarz, and Son Dao-Trong. 2010. System and method for a floating point unit with feedback prior to normalization and rounding. US Patent 7,730,117.","journal-title":"US Patent"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/SCAM.2013.6648190"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3337801.3337809"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1236463.1236468"},{"volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference. IEEE","author":"Gort Marcel","key":"e_1_2_1_22_1","unstructured":"Marcel Gort and Jason H. Anderson . 2013. Range and bitmask analysis for hardware optimization in high-level synthesis . In Proceedings of the Asia and South Pacific Design Automation Conference. IEEE , Los Alamitos, CA, 773--779. Marcel Gort and Jason H. Anderson. 2013. Range and bitmask analysis for hardware optimization in high-level synthesis. In Proceedings of the Asia and South Pacific Design Automation Conference. IEEE, Los Alamitos, CA, 773--779."},{"key":"e_1_2_1_23_1","first-page":"11","article-title":"Lower bounds for constant multiplication problems","volume":"54","author":"Gustafsson Oscar","year":"2007","unstructured":"Oscar Gustafsson . 2007 . Lower bounds for constant multiplication problems . ACM Transactions on Circuits and Systems II: Express Briefs 54 , 11 (Nov. 2007), 974--978. Oscar Gustafsson. 2007. Lower bounds for constant multiplication problems. ACM Transactions on Circuits and Systems II: Express Briefs 54, 11 (Nov. 2007), 974--978.","journal-title":"ACM Transactions on Circuits and Systems II: Express Briefs"},{"key":"e_1_2_1_24_1","unstructured":"James Hrica. 2012. Floating-Point Design with Vivado HLS. Application Note. Xilinx.  James Hrica. 2012. Floating-Point Design with Vivado HLS. Application Note. Xilinx."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2629547"},{"key":"e_1_2_1_26_1","first-page":"2011","article-title":"C11 Standard","volume":"9899","author":"ISO.","year":"2011","unstructured":"ISO. 2011 . C11 Standard . ISO\/IEC 9899 : 2011 . ISO. ISO. 2011. C11 Standard. ISO\/IEC 9899:2011. ISO.","journal-title":"ISO\/IEC"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2532874"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2007.25"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00607-010-0127-7"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2631630"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.841125"},{"volume-title":"Building an Optimizing Compiler","author":"Morgan Robert","key":"e_1_2_1_32_1","unstructured":"Robert Morgan . 1998. Building an Optimizing Compiler . Digital Press . Robert Morgan. 1998. Building an Optimizing Compiler. Digital Press."},{"key":"e_1_2_1_33_1","unstructured":"Steven Muchnick. 1997. Advanced Compiler Design Implementation. Morgan Kaufmann.  Steven Muchnick. 1997. Advanced Compiler Design Implementation. Morgan Kaufmann."},{"key":"e_1_2_1_34_1","volume-title":"Handbook of Floating-Point Arithmetic","author":"Muller Jean-Michel","unstructured":"Jean-Michel Muller , Nicolas Brunie , Florent de Dinechin , Claude-Pierre Jeannerod , Mioara Joldes , Vincent Lef\u00e8vre , Guillaume Melquiond , Nathalie Revol , and Serge Torres . 2018. Handbook of Floating-Point Arithmetic ( 2 nd ed.). Birkhauser , Boston, MA . Jean-Michel Muller, Nicolas Brunie, Florent de Dinechin, Claude-Pierre Jeannerod, Mioara Joldes, Vincent Lef\u00e8vre, Guillaume Melquiond, Nathalie Revol, and Serge Torres. 2018. Handbook of Floating-Point Arithmetic (2nd ed.). Birkhauser, Boston, MA.","edition":"2"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339189"},{"key":"e_1_2_1_37_1","volume-title":"Retrieved","author":"Pouchet Louis-No\u00ebl","year":"2012","unstructured":"Louis-No\u00ebl Pouchet . 2012 . Polybench: The Polyhedral Benchmark Suite . Retrieved March 25, 2019 from https:\/\/dl.acm.org\/doi\/abs\/10.1145\/1240233.1240234. Louis-No\u00ebl Pouchet. 2012. Polybench: The Polyhedral Benchmark Suite. Retrieved March 25, 2019 from https:\/\/dl.acm.org\/doi\/abs\/10.1145\/1240233.1240234."},{"key":"e_1_2_1_38_1","first-page":"3","article-title":"Detection of scans","volume":"15","author":"Redon Xavier","year":"2000","unstructured":"Xavier Redon and Paul Feautrier . 2000 . Detection of scans . Parallel Algorithms and Applictations 15 , 3 \u2013 4 (2000), 229--263. Xavier Redon and Paul Feautrier. 2000. Detection of scans. Parallel Algorithms and Applictations 15, 3\u20134 (2000), 229--263.","journal-title":"Parallel Algorithms and Applictations"},{"key":"e_1_2_1_39_1","unstructured":"Olivier Sentieys Daniel Menard David Novo and Karthick Parashar. 2014. Automatic fixed-point conversion: A gateway to high-level power optimization. Tutorial presented at the IEEE\/ACM Design Automation and Test in Europe Conference.  Olivier Sentieys Daniel Menard David Novo and Karthick Parashar. 2014. Automatic fixed-point conversion: A gateway to high-level power optimization. Tutorial presented at the IEEE\/ACM Design Automation and Test in Europe Conference."},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00038"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2153853"},{"key":"e_1_2_1_42_1","volume-title":"CCSD HAL. Retrieved","author":"Uguen Yohann","year":"2017","unstructured":"Yohann Uguen and Florent de Dinechin . 2017 . Design-space exploration for the Kulisch accumulator . CCSD HAL. Retrieved January 29, 2020 from https:\/\/hal.archives-ouvertes.fr\/hal-01488916v2. Yohann Uguen and Florent de Dinechin. 2017. Design-space exploration for the Kulisch accumulator. CCSD HAL. Retrieved January 29, 2020 from https:\/\/hal.archives-ouvertes.fr\/hal-01488916v2."},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056792"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00026"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2707488"},{"volume-title":"High-Performance Computing Using FPGAs","author":"Vanderbauwhede Wim","key":"e_1_2_1_46_1","unstructured":"Wim Vanderbauwhede and Khaled Benkrid . 2013. High-Performance Computing Using FPGAs . Vol. 3 . Springer . Wim Vanderbauwhede and Khaled Benkrid. 2013. High-Performance Computing Using FPGAs. Vol. 3. Springer."},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1240233.1240234"},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.3390\/electronics6040101"},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.5555\/960089.2813470"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3377403","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3377403","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:33:17Z","timestamp":1750199597000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3377403"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3,4]]},"references-count":49,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2020,3,31]]}},"alternative-id":["10.1145\/3377403"],"URL":"https:\/\/doi.org\/10.1145\/3377403","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"type":"print","value":"1544-3566"},{"type":"electronic","value":"1544-3973"}],"subject":[],"published":{"date-parts":[[2020,3,4]]},"assertion":[{"value":"2019-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-03-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}