{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,7]],"date-time":"2025-07-07T04:24:28Z","timestamp":1751862268500,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,5,25]],"date-time":"2020-05-25T00:00:00Z","timestamp":1590364800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Deutsche Forschungsgemeinschaft (DFG, German Research Foundation)","award":["146371743"],"award-info":[{"award-number":["146371743"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,5,25]]},"DOI":"10.1145\/3378678.3391878","type":"proceedings-article","created":{"date-parts":[[2020,5,26]],"date-time":"2020-05-26T00:21:35Z","timestamp":1590452495000},"page":"26-31","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs"],"prefix":"10.1145","author":[{"given":"Christian","family":"Heidorn","sequence":"first","affiliation":[{"name":"Friedrich-Alexander University Erlangen-N\u00fcrnberg (FAU), Germany"}]},{"given":"Frank","family":"Hannig","sequence":"additional","affiliation":[{"name":"Friedrich-Alexander University Erlangen-N\u00fcrnberg (FAU), Germany"}]},{"given":"J\u00fcrgen","family":"Teich","sequence":"additional","affiliation":[{"name":"Friedrich-Alexander University Erlangen-N\u00fcrnberg (FAU), Germany"}]}],"member":"320","published-online":{"date-parts":[[2020,5,25]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"807","volume-title":"Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2019","author":"Mingyu","year":"2019","unstructured":"Mingyu Gao et al. \"TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators \". In: Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2019 , Providence, RI, USA , April 13-17, 2019 . 2019, pp. 807 -- 820 . Mingyu Gao et al. \"TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators\". In: Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2019, Providence, RI, USA, April 13-17, 2019. 2019, pp. 807--820."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2761740"},{"key":"e_1_3_2_1_3_1","first-page":"1","volume-title":"ISCA 2017","author":"Norman","year":"2017","unstructured":"Norman P. Jouppi et al. \"In-Datacenter Performance Analysis of a Tensor Processing Unit \". In: ISCA 2017 , Toronto, Canada , June 24-28, 2017 . 2017, pp. 1 -- 12 . Norman P. Jouppi et al. \"In-Datacenter Performance Analysis of a Tensor Processing Unit\". In: ISCA 2017, Toronto, Canada, June 24-28, 2017. 2017, pp. 1--12."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2797600"},{"key":"e_1_3_2_1_5_1","first-page":"1811","article-title":"SCALE-Sim: Systolic CNN Accelerator","author":"Ananda Samajdar","year":"2019","unstructured":"Ananda Samajdar et al . \" SCALE-Sim: Systolic CNN Accelerator \". In: The Computing Research Repository (CoRR) ( Feb. 2, 2019 ). arXiv: 1811 .02883v2 [cs.DC]. Ananda Samajdar et al. \"SCALE-Sim: Systolic CNN Accelerator\". In: The Computing Research Repository (CoRR) (Feb. 2, 2019). arXiv: 1811.02883v2 [cs.DC].","journal-title":"The Computing Research Repository (CoRR)"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"e_1_3_2_1_7_1","first-page":"161","volume-title":"Proceedings of the 2015 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","author":"Chen","year":"2015","unstructured":"Chen Zhang et al. \"Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks \". In: Proceedings of the 2015 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays , Monterey, CA, USA , February 22-24, 2015 . 2015, pp. 161 -- 170 . Chen Zhang et al. \"Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks\". In: Proceedings of the 2015 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015. 2015, pp. 161--170."},{"key":"e_1_3_2_1_8_1","volume-title":"54th Annual Design Automation Conference, DAC 2017","author":"Xuechao","year":"2017","unstructured":"Xuechao Wei et al. \"Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs \". In: 54th Annual Design Automation Conference, DAC 2017 , Austin, TX, USA , June 18-22, 2017 . 2017, 29:1--29:6. Xuechao Wei et al. \"Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs\". In: 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017. 2017, 29:1--29:6."},{"key":"e_1_3_2_1_9_1","first-page":"1809","article-title":"DNN Dataflow Choice Is Overrated","author":"Xuan Yang","year":"2018","unstructured":"Xuan Yang et al . \" DNN Dataflow Choice Is Overrated \". In: The Computing Research Repository (CoRR) ( Sept. 10, 2018 ). arXiv: 1809 .04070v1 [cs.DC]. Xuan Yang et al. \"DNN Dataflow Choice Is Overrated\". In: The Computing Research Repository (CoRR) (Sept. 10, 2018). arXiv: 1809.04070v1 [cs.DC].","journal-title":"The Computing Research Repository (CoRR)"},{"key":"e_1_3_2_1_10_1","volume-title":"ACM Trans. Embedded Comput. Syst. 18.5s","author":"Shail Dave","year":"2019","unstructured":"Shail Dave et al. \" dMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators \". In: ACM Trans. Embedded Comput. Syst. 18.5s ( 2019 ), 70: 1--70:27. Shail Dave et al. \"dMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators\". In: ACM Trans. Embedded Comput. Syst. 18.5s (2019), 70:1--70:27."},{"key":"e_1_3_2_1_11_1","volume-title":"49th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 2016","author":"Manoj","year":"2016","unstructured":"Manoj Alwani et al. \"Fused-layer CNN accelerators \". In: 49th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 2016 , Taipei, Taiwan , October 15-19, 2016 . 2016, 22:1--22:12. Manoj Alwani et al. \"Fused-layer CNN accelerators\". In: 49th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 2016, Taipei, Taiwan, October 15-19, 2016. 2016, 22:1--22:12."},{"key":"e_1_3_2_1_12_1","first-page":"1804","article-title":"BrainSlug: Transparent Acceleration of Deep Learning Through Depth-First Parallelism","author":"Nicolas Weber","year":"2018","unstructured":"Nicolas Weber et al . \" BrainSlug: Transparent Acceleration of Deep Learning Through Depth-First Parallelism \". In: The Computing Research Repository (CoRR) ( Apr. 23, 2018 ). arXiv: 1804 .08378v1 [cs.DC]. Nicolas Weber et al. \"BrainSlug: Transparent Acceleration of Deep Learning Through Depth-First Parallelism\". In: The Computing Research Repository (CoRR) (Apr. 23, 2018). arXiv: 1804.08378v1 [cs.DC].","journal-title":"The Computing Research Repository (CoRR)"},{"key":"e_1_3_2_1_13_1","first-page":"253","volume-title":"20th International Symposium on Quality Electronic Design, ISQED 2019","author":"Kenshu","year":"2019","unstructured":"Kenshu Seto et al. \"Small Memory Footprint Neural Network Accelerators \". In: 20th International Symposium on Quality Electronic Design, ISQED 2019 , Santa Clara, CA, USA , March 6-7, 2019 . 2019, pp. 253 -- 258 . Kenshu Seto et al. \"Small Memory Footprint Neural Network Accelerators\". In: 20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, CA, USA, March 6-7, 2019. 2019, pp. 253--258."},{"key":"e_1_3_2_1_14_1","first-page":"541","volume-title":"JCP","author":"Christian","year":"2019","unstructured":"Christian Heidorn et al. \"Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays \". In: JCP ( 2019 ), pp. 541 -- 556 . Christian Heidorn et al. \"Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays\". In: JCP (2019), pp. 541--556."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-662-04267-0","volume-title":"Computer architecture - complexity and correctness","author":"M\u00fcller Silvia M.","year":"2000","unstructured":"Silvia M. M\u00fcller and Wolfgang J. Paul . Computer architecture - complexity and correctness . Springer , 2000 . Silvia M. M\u00fcller and Wolfgang J. Paul. Computer architecture - complexity and correctness. Springer, 2000."},{"key":"e_1_3_2_1_16_1","first-page":"1106","volume-title":"Advances in Neural Information Processing Systems 25: Proceedings of a meeting held","author":"Krizhevsky Alex","year":"2012","unstructured":"Alex Krizhevsky , Ilya Sutskever , and Geoffrey E. Hinton . \"ImageNet Classification with Deep Convolutional Neural Networks \". In: Advances in Neural Information Processing Systems 25: Proceedings of a meeting held December 3-6, 2012 , Lake Tahoe, Nevada, United States. 2012, pp. 1106 -- 1114 . Alex Krizhevsky, Ilya Sutskever, and Geoffrey E. Hinton. \"ImageNet Classification with Deep Convolutional Neural Networks\". In: Advances in Neural Information Processing Systems 25: Proceedings of a meeting held December 3-6, 2012, Lake Tahoe, Nevada, United States. 2012, pp. 1106--1114."},{"key":"e_1_3_2_1_17_1","first-page":"1704","article-title":"MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications","author":"Howard Andrew G.","year":"2017","unstructured":"Andrew G. Howard . \" MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications \". In: The Computing Research Repository (CoRR) ( Apr. 17, 2017 ). arXiv: 1704 .04861v1 [cs. CV]. Andrew G. Howard et al. \"MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications\". In: The Computing Research Repository (CoRR) (Apr. 17, 2017). arXiv: 1704.04861v1 [cs. CV].","journal-title":"The Computing Research Repository (CoRR)"}],"event":{"name":"SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","EDAA European Design Automation Association"],"location":"St. Goar Germany","acronym":"SCOPES '20"},"container-title":["Proceedings of the 23th International Workshop on Software and Compilers for Embedded Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3378678.3391878","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3378678.3391878","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:41:19Z","timestamp":1750200079000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3378678.3391878"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,5,25]]},"references-count":17,"alternative-id":["10.1145\/3378678.3391878","10.1145\/3378678"],"URL":"https:\/\/doi.org\/10.1145\/3378678.3391878","relation":{},"subject":[],"published":{"date-parts":[[2020,5,25]]},"assertion":[{"value":"2020-05-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}