{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,13]],"date-time":"2026-04-13T20:34:47Z","timestamp":1776112487803,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":34,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,10,20]],"date-time":"2020-10-20T00:00:00Z","timestamp":1603152000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"NSF","award":["CNS 1505773, CNS 1822332"],"award-info":[{"award-number":["CNS 1505773, CNS 1822332"]}]},{"name":"Synergy: Collaborative: CPS-Security: End-to-End Security for the Internet of Things"},{"name":"CONIX Research Center, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA"},{"name":"Paul and Judy Gray Alumni Presidential Chair in Engineering Excellence"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,10,20]]},"DOI":"10.1145\/3379337.3415860","type":"proceedings-article","created":{"date-parts":[[2020,10,16]],"date-time":"2020-10-16T19:01:43Z","timestamp":1602874903000},"page":"529-540","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Polymorphic Blocks: Unifying High-level Specification and Low-level Control for Circuit Board Design"],"prefix":"10.1145","author":[{"given":"Richard","family":"Lin","sequence":"first","affiliation":[{"name":"University of California, Berkeley, Berkeley, CA, USA"}]},{"given":"Rohit","family":"Ramesh","sequence":"additional","affiliation":[{"name":"University of California, Berkeley, Berkeley, CA, USA"}]},{"given":"Connie","family":"Chi","sequence":"additional","affiliation":[{"name":"University of California, Berkeley, Berkeley, CA, USA"}]},{"given":"Nikhil","family":"Jain","sequence":"additional","affiliation":[{"name":"University of California, Berkeley, Berkeley, CA, USA"}]},{"given":"Ryan","family":"Nuqui","sequence":"additional","affiliation":[{"name":"University of California, Berkeley, Berkeley, CA, USA"}]},{"given":"Prabal","family":"Dutta","sequence":"additional","affiliation":[{"name":"University of California, Berkeley, Berkeley, CA, USA"}]},{"given":"Bj\u00f6rn","family":"Hartmann","sequence":"additional","affiliation":[{"name":"University of California, Berkeley, Berkeley, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2020,10,20]]},"reference":[{"key":"e_1_3_2_2_1_1","volume-title":"https:\/\/www.altium.com\/altium-designer\/","author":"Designer Altium","year":"2020"},{"key":"e_1_3_2_2_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/3126594.3126637"},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IROS.2016.7759349"},{"key":"e_1_3_2_2_4_1","volume-title":"36th Design Automation Conference. 21--25","author":"Christen Ernst","year":"1999"},{"key":"e_1_3_2_2_5_1","volume-title":"Circuit Design App for Makers- circuito.io. (Feb","year":"2020"},{"key":"e_1_3_2_2_6_1","volume-title":"Proceedings of the International Conference on Computer-Aided Design (ICCAD '13)","author":"Crossley J."},{"key":"e_1_3_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2984511.2984566"},{"key":"e_1_3_2_2_8_1","unstructured":"EDASolver. 2020. EDASolver - Automatic component selection and pin matching. (2020). https:\/\/edasolver.com  EDASolver. 2020. EDASolver - Automatic component selection and pin matching. (2020). https:\/\/edasolver.com"},{"key":"e_1_3_2_2_9_1","unstructured":"Eclipse Foundation. 2020. Eclipse Layout Kernel. (2020). https:\/\/www.eclipse.org\/elk\/  Eclipse Foundation. 2020. Eclipse Layout Kernel. (2020). https:\/\/www.eclipse.org\/elk\/"},{"key":"e_1_3_2_2_10_1","volume-title":"www.gumstix.com\/geppetto\/","year":"2018"},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.44506"},{"key":"e_1_3_2_2_12_1","unstructured":"Accellera System Initiative. 2014. Verilog-AMS Language Reference Manual. (2014).  Accellera System Initiative. 2014. Verilog-AMS Language Reference Manual. (2014)."},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203780"},{"key":"e_1_3_2_2_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/3313831.3376761"},{"key":"e_1_3_2_2_15_1","unstructured":"KiCad. 2020. KiCad EDA. (2020). http:\/\/kicad-pcb.org\/  KiCad. 2020. KiCad EDA. (2020). http:\/\/kicad-pcb.org\/"},{"key":"e_1_3_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3290605.3300407"},{"key":"e_1_3_2_2_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1517664.1517735"},{"key":"e_1_3_2_2_18_1","volume-title":"https:\/\/www.ultralibrarian.com\/","author":"Librarian Ultra","year":"2020"},{"key":"e_1_3_2_2_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/3290605.3300513"},{"key":"e_1_3_2_2_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3290605.3300633"},{"key":"e_1_3_2_2_21_1","unstructured":"Mentor. 2020a. Error Reduction in the Design Definition Phase. (2020). https:\/\/www.mentor.com\/pcb\/multimedia\/player\/error-reduction-in-the-design-definition-phase-0db48520--5d96--43ba-a208-d10513b742c6  Mentor. 2020a. Error Reduction in the Design Definition Phase. (2020). https:\/\/www.mentor.com\/pcb\/multimedia\/player\/error-reduction-in-the-design-definition-phase-0db48520--5d96--43ba-a208-d10513b742c6"},{"key":"e_1_3_2_2_22_1","unstructured":"Mentor. 2020b. Get to Market Fast and First with Reusable Circuit Blocks. (2020). https:\/\/www.mentor.com\/pcb\/resources\/overview\/get-to-market-fast-and-first-with-reusable-circuit-blocks-981762c9--485a-416f-877c-b6dbf7622c45  Mentor. 2020b. Get to Market Fast and First with Reusable Circuit Blocks. (2020). https:\/\/www.mentor.com\/pcb\/resources\/overview\/get-to-market-fast-and-first-with-reusable-circuit-blocks-981762c9--485a-416f-877c-b6dbf7622c45"},{"key":"e_1_3_2_2_23_1","volume-title":"https:\/\/www.mentor.com\/pcb\/xpedition\/","author":"Enterprise Xpedition","year":"2020"},{"key":"e_1_3_2_2_24_1","unstructured":"Mentor. 2020d. Xpedition Valydate Schematic Analysis. (2020). https:\/\/www.mentor.com\/pcb\/xpedition\/schematic-analysis\/  Mentor. 2020d. Xpedition Valydate Schematic Analysis. (2020). https:\/\/www.mentor.com\/pcb\/xpedition\/schematic-analysis\/"},{"key":"e_1_3_2_2_25_1","unstructured":"Brant Nelson Brad Riching and Josh Mangelson. 2012. Using a Custom-Built HDL for Printed Circuit Board Design Capture. PCB West 2012 Presentation. (2012).  Brant Nelson Brad Riching and Josh Mangelson. 2012. Using a Custom-Built HDL for Printed Circuit Board Design Capture. PCB West 2012 Presentation. (2012)."},{"key":"e_1_3_2_2_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3083157.3083159"},{"key":"e_1_3_2_2_27_1","unstructured":"Mitchel Resnick Brad Myers Kumiyo Nakakoji Ben Shneiderman Randy Pausch Ted Selker and Mike Eisenberg. 2005. Design principles for tools to support creative thinking. (2005).  Mitchel Resnick Brad Myers Kumiyo Nakakoji Ben Shneiderman Randy Pausch Ted Selker and Mike Eisenberg. 2005. Design principles for tools to support creative thinking. (2005)."},{"key":"e_1_3_2_2_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1323688.1323689"},{"key":"e_1_3_2_2_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3126594.3126618"},{"key":"e_1_3_2_2_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/3290605.3300278"},{"key":"e_1_3_2_2_31_1","volume-title":"https:\/\/tabula.technology\/","year":"2020"},{"key":"e_1_3_2_2_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3242587.3242591"},{"key":"e_1_3_2_2_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/3126594.3126646"},{"key":"e_1_3_2_2_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/3126594.3126634"}],"event":{"name":"UIST '20: The 33rd Annual ACM Symposium on User Interface Software and Technology","location":"Virtual Event USA","acronym":"UIST '20","sponsor":["SIGGRAPH ACM Special Interest Group on Computer Graphics and Interactive Techniques","SIGCHI ACM Special Interest Group on Computer-Human Interaction"]},"container-title":["Proceedings of the 33rd Annual ACM Symposium on User Interface Software and Technology"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3379337.3415860","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3379337.3415860","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3379337.3415860","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:38:50Z","timestamp":1750199930000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3379337.3415860"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10,20]]},"references-count":34,"alternative-id":["10.1145\/3379337.3415860","10.1145\/3379337"],"URL":"https:\/\/doi.org\/10.1145\/3379337.3415860","relation":{},"subject":[],"published":{"date-parts":[[2020,10,20]]},"assertion":[{"value":"2020-10-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}