{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:25:08Z","timestamp":1750220708878,"version":"3.41.0"},"reference-count":38,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2020,5,18]],"date-time":"2020-05-18T00:00:00Z","timestamp":1589760000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"European Regional Development Fund - FEDER"},{"name":"Spanish Government","award":["TEC2016-80549-R and TEC2017-87052-P"],"award-info":[{"award-number":["TEC2016-80549-R and TEC2017-87052-P"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2020,7,31]]},"abstract":"<jats:p>The design of near future cryptocircuits will require greater performance characteristics in order to be implemented in devices with very limited resources for secure applications. Considering the security against differential power side-channel attacks (DPA), explorations of different implementations of dual-precharge logic gates with advanced and emerging technologies, using nanometric FinFET and Tunnel FET transistors, are proposed aiming to maintain or even improve the security levels obtained by current Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) technologies and reducing the resources needed for the implementations. As case study, dual-precharge logic primitives have been designed and included in the 4-bit substitution box of PRIDE algorithm, measuring the performance and evaluating the security through simulation-based Differential Power Analysis (DPA) attacks for each implementation. Extensive electrical simulations with predictive Predictive Transistor model on scaled 16nm and 22nm MOSFET, 16nm and 20nm FinFET, and 20nm Tunnel Field Effect Transistor (TFET) demonstrate a clear evolution of security and performances with respect to current 90nm MOSFET implementations, providing FinFET as fastest solutions with a delay 3.7 times better than conventional proposals, but TFET being the best candidate for future cryptocircuits in terms of average power consumption (x0.02 times compared with conventional technologies) and security in some orders of magnitude.<\/jats:p>","DOI":"10.1145\/3381857","type":"journal-article","created":{"date-parts":[[2020,5,21]],"date-time":"2020-05-21T22:24:11Z","timestamp":1590099851000},"page":"1-16","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies"],"prefix":"10.1145","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0003-3318","authenticated-orcid":false,"given":"I. M.","family":"Delgado-Lozano","sequence":"first","affiliation":[{"name":"Tampere University, Tampere, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Tena-S\u00e1nchez","sequence":"additional","affiliation":[{"name":"Instituto de Microelectr\u00f3nica de Sevilla (IMSE-CNM), CSIC\/Universidad de Sevilla, Seville, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"N\u00fa\u00f1ez","sequence":"additional","affiliation":[{"name":"Instituto de Microelectr\u00f3nica de Sevilla (IMSE-CNM), CSIC\/Universidad de Sevilla, Seville, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A. J.","family":"Acosta","sequence":"additional","affiliation":[{"name":"Instituto de Microelectr\u00f3nica de Sevilla (IMSE-CNM), CSIC\/Universidad de Sevilla, Seville, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,5,18]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Gregor Leander, Christof Paar, and Tolga Yal\u00e7in.","author":"Albrecht Martin R.","year":"2014","unstructured":"Martin R. Albrecht , Benedikt Driessen , Elif Bilge Kavun , Gregor Leander, Christof Paar, and Tolga Yal\u00e7in. 2014 . Block ciphers\u2014Focus on the linear layer (feat. PRIDE). In Lecture Notes in Computer Science, 8616 LNCS (Ed.). Springer , 57--76. DOI:https:\/\/doi.org\/10.1007\/978-3-662-44371-2_4 10.1007\/978-3-662-44371-2_4 Martin R. Albrecht, Benedikt Driessen, Elif Bilge Kavun, Gregor Leander, Christof Paar, and Tolga Yal\u00e7in. 2014. Block ciphers\u2014Focus on the linear layer (feat. PRIDE). In Lecture Notes in Computer Science, 8616 LNCS (Ed.). Springer, 57--76. DOI:https:\/\/doi.org\/10.1007\/978-3-662-44371-2_4"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2278350"},{"key":"e_1_2_1_3_1","first-page":"21","article-title":"Improving speed of tunnel FETs logic circuits","volume":"51","author":"Jos\u00e9 Mar\u00eda","year":"2015","unstructured":"Mar\u00eda Jos\u00e9 , Avedillo and Juan N\u00fa\u00f1ez . 2015 . Improving speed of tunnel FETs logic circuits . IEEE Journal on Emerging and Selected Topics in Circuits and Systems 51 , 21 (Oct. 2015), 1702--1704. DOI:https:\/\/doi.org\/10.1049\/el.2015.2416 10.1049\/el.2015.2416 Mar\u00eda Jos\u00e9, Avedillo and Juan N\u00fa\u00f1ez. 2015. Improving speed of tunnel FETs logic circuits. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 51, 21 (Oct. 2015), 1702--1704. DOI:https:\/\/doi.org\/10.1049\/el.2015.2416","journal-title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2016.2559159"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/NTMS.2011.5720614"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2713483"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878344"},{"key":"e_1_2_1_8_1","first-page":"3","article-title":"Analysis of electromagnetic information leakage from cryptographic devices with different physical structures","volume":"55","author":"Hayashi Yu-Ichi","year":"2013","unstructured":"Yu-Ichi Hayashi , Naofumi Homma , Takaaki Mizuki , Takafumi Aoki , Hideaki Sone , Laurent Sauvage , and Jean-Luc Danger . 2013 . Analysis of electromagnetic information leakage from cryptographic devices with different physical structures . IEEE Transactions on Electromagnetic Compatibility 55 , 3 (June 2013), 571--580. DOI:https:\/\/doi.org\/10.1109\/TEMC.2012.2227486 10.1109\/TEMC.2012.2227486 Yu-Ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Laurent Sauvage, and Jean-Luc Danger. 2013. Analysis of electromagnetic information leakage from cryptographic devices with different physical structures. IEEE Transactions on Electromagnetic Compatibility 55, 3 (June 2013), 571--580. DOI:https:\/\/doi.org\/10.1109\/TEMC.2012.2227486","journal-title":"IEEE Transactions on Electromagnetic Compatibility"},{"key":"e_1_2_1_9_1","volume-title":"IEEE International Roadmap for Devices and Systems. Retrieved","author":"IEEE.","year":"2019","unstructured":"IEEE. [n.d.]. IEEE International Roadmap for Devices and Systems. Retrieved April 8, 2019 from https:\/\/irds.ieee.org\/. IEEE. [n.d.]. IEEE International Roadmap for Devices and Systems. Retrieved April 8, 2019 from https:\/\/irds.ieee.org\/."},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of International Cryptology Conference (CRYPTO\u201903)","author":"Ishai Yuval","year":"2003","unstructured":"Yuval Ishai , Amit Sahai , and David Wagner . 2003 . Private circuits: Private circuits securing hardware against probing attacks . In Proceedings of International Cryptology Conference (CRYPTO\u201903) . Springer, Berlin, 463--481. Yuval Ishai, Amit Sahai, and David Wagner. 2003. Private circuits: Private circuits securing hardware against probing attacks. In Proceedings of International Cryptology Conference (CRYPTO\u201903). Springer, Berlin, 463--481."},{"volume-title":"Three phase dynamic current mode logic: A more secure DyCML to achieve a more balanced power consumption","author":"Kim Hyunmin","key":"e_1_2_1_11_1","unstructured":"Hyunmin Kim , Vladimir Rozic , and Ingrid Verbauwhede . 2012. Three phase dynamic current mode logic: A more secure DyCML to achieve a more balanced power consumption . Springer , Berlin , 68--81. DOI:https:\/\/doi.org\/10.1007\/978-3-642-35416-8_6 10.1007\/978-3-642-35416-8_6 Hyunmin Kim, Vladimir Rozic, and Ingrid Verbauwhede. 2012. Three phase dynamic current mode logic: A more secure DyCML to achieve a more balanced power consumption. Springer, Berlin, 68--81. DOI:https:\/\/doi.org\/10.1007\/978-3-642-35416-8_6"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-68697-5_9"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_25"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2883899"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2592967"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1080\/23742917.2016.1231523"},{"key":"e_1_2_1_17_1","volume-title":"Universal analytic model for tunnel FET circuit simulation. Solid-State Electronics 108 (June","author":"Lu Hao","year":"2015","unstructured":"Hao Lu , David Esseni , and Alan Seabaugh . 2015. Universal analytic model for tunnel FET circuit simulation. Solid-State Electronics 108 (June 2015 ), 110--117. DOI:https:\/\/doi.org\/10.1016\/j.sse.2014.12.002 10.1016\/j.sse.2014.12.002 Hao Lu, David Esseni, and Alan Seabaugh. 2015. Universal analytic model for tunnel FET circuit simulation. Solid-State Electronics 108 (June 2015), 110--117. DOI:https:\/\/doi.org\/10.1016\/j.sse.2014.12.002"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2014.2326622"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICITST.2015.7412116"},{"volume-title":"Power Analysis Attacks: Revealing the Secret of Smart Cards","author":"Mangard Stefan","key":"e_1_2_1_20_1","unstructured":"Stefan Mangard , Elisabeth Oswald , and Thomas Popp . 2007. Power Analysis Attacks: Revealing the Secret of Smart Cards . Springer . Stefan Mangard, Elisabeth Oswald, and Thomas Popp. 2007. Power Analysis Attacks: Revealing the Secret of Smart Cards. Springer."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2014.2361054"},{"key":"e_1_2_1_22_1","first-page":"2","article-title":"Design of adiabatic dynamic differential logic for DPA-resistant secure integrated circuits","volume":"1","author":"Morrison Matthew A.","year":"2017","unstructured":"Matthew A. Morrison , Nagarajan Ranganathan , and Jay Ligatti . 2017 . Design of adiabatic dynamic differential logic for DPA-resistant secure integrated circuits . IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1 , 2 (April 2017), 88--107. DOI:https:\/\/doi.org\/10.1109\/TVLSI.2014.2342034 10.1109\/TVLSI.2014.2342034 Matthew A. Morrison, Nagarajan Ranganathan, and Jay Ligatti. 2017. Design of adiabatic dynamic differential logic for DPA-resistant secure integrated circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1, 2 (April 2017), 88--107. DOI:https:\/\/doi.org\/10.1109\/TVLSI.2014.2342034","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-13039-2_22"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1007\/11502760_29"},{"volume-title":"Fundamentals of Tunnel Field Effect Transistors","author":"Saurabh Sneh","key":"e_1_2_1_25_1","unstructured":"Sneh Saurabh and Mamidala Jagadesh . 2016. Fundamentals of Tunnel Field Effect Transistors . CRC Press . Sneh Saurabh and Mamidala Jagadesh. 2016. Fundamentals of Tunnel Field Effect Transistors. CRC Press."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_7"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228414"},{"key":"e_1_2_1_28_1","first-page":"271","article-title":"Security analysis of tunnel field-effect transistor for low power hardware","volume":"8","author":"Taheri Shayan","year":"2017","unstructured":"Shayan Taheri and Jiann-Shiun Yuan . 2017 . Security analysis of tunnel field-effect transistor for low power hardware . International Journal of Computer Science and Information Technologies (IJCSIT) 8 , 2 (2017), 271 -- 275 . www.ijcsit.com. Shayan Taheri and Jiann-Shiun Yuan. 2017. Security analysis of tunnel field-effect transistor for low power hardware. International Journal of Computer Science and Information Technologies (IJCSIT) 8, 2 (2017), 271--275. www.ijcsit.com.","journal-title":"International Journal of Computer Science and Information Technologies (IJCSIT)"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2014.2315878"},{"volume-title":"2018 Conference on Design of Circuits and Integrated Systems (DCIS\u201918)","author":"Tena-S\u00e1nchez Erica","key":"e_1_2_1_30_1","unstructured":"Erica Tena-S\u00e1nchez , Ignacio M. Delgado-Lozano , Juan N\u00fa\u00f1ez , and Antonio J. Acosta . 2018. Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits . In 2018 Conference on Design of Circuits and Integrated Systems (DCIS\u201918) . Erica Tena-S\u00e1nchez, Ignacio M. Delgado-Lozano, Juan N\u00fa\u00f1ez, and Antonio J. Acosta. 2018. Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. In 2018 Conference on Design of Circuits and Integrated Systems (DCIS\u201918)."},{"key":"e_1_2_1_31_1","volume-title":"European Solid-State Circuits Conference (ESSCIRC). IEEE, 403--406","author":"Tiri Kris","year":"2002","unstructured":"Kris Tiri , Moonmoon Akmal , and Ingrid Verbauwhede . 2002 . A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards . In European Solid-State Circuits Conference (ESSCIRC). IEEE, 403--406 . Kris Tiri, Moonmoon Akmal, and Ingrid Verbauwhede. 2002. A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards. In European Solid-State Circuits Conference (ESSCIRC). IEEE, 403--406."},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_26"},{"volume-title":"Design, Automation and Test in Europe (DATE\u201904)","author":"Tiri Kris","key":"e_1_2_1_33_1","unstructured":"Kris Tiri and Ingrid Verbauwhede . 2004. A logic level design methodlogy for a secure DPA resistant ASIC or FPGA implementation . In Design, Automation and Test in Europe (DATE\u201904) . IEEE , 246--251. DOI:https:\/\/doi.org\/10.1109\/DATE.2004.1268856 10.1109\/DATE.2004.1268856 Kris Tiri and Ingrid Verbauwhede. 2004. A logic level design methodlogy for a secure DPA resistant ASIC or FPGA implementation. In Design, Automation and Test in Europe (DATE\u201904). IEEE, 246--251. DOI:https:\/\/doi.org\/10.1109\/DATE.2004.1268856"},{"volume-title":"Design, Automation and Test in Europe (DATE\u201905)","author":"Tiri Kris","key":"e_1_2_1_34_1","unstructured":"Kris Tiri and Ingrid Verbauwhede . 2005. Design method for constant power consumption of differential logic circuits . In Design, Automation and Test in Europe (DATE\u201905) . IEEE , 628--633. DOI:https:\/\/doi.org\/10.1109\/DATE.2005.113 10.1109\/DATE.2005.113 Kris Tiri and Ingrid Verbauwhede. 2005. Design method for constant power consumption of differential logic circuits. In Design, Automation and Test in Europe (DATE\u201905). IEEE, 628--633. DOI:https:\/\/doi.org\/10.1109\/DATE.2005.113"},{"volume-title":"Design, Automation and Test in Europe (DATE\u201905)","author":"Tiri Kris","key":"e_1_2_1_35_1","unstructured":"Kris Tiri and Ingrid Verbauwhede . 2005. A VLSI design flow for secure side-channel attack resistant ICs . In Design, Automation and Test in Europe (DATE\u201905) . IEEE , 58--63. DOI:https:\/\/doi.org\/10.1109\/DATE.2005.44 10.1109\/DATE.2005.44 Kris Tiri and Ingrid Verbauwhede. 2005. A VLSI design flow for secure side-channel attack resistant ICs. In Design, Automation and Test in Europe (DATE\u201905). IEEE, 58--63. DOI:https:\/\/doi.org\/10.1109\/DATE.2005.44"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001385"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000502.2000503"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.91"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3381857","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3381857","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:33:07Z","timestamp":1750199587000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3381857"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,5,18]]},"references-count":38,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2020,7,31]]}},"alternative-id":["10.1145\/3381857"],"URL":"https:\/\/doi.org\/10.1145\/3381857","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2020,5,18]]},"assertion":[{"value":"2019-05-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-02-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-05-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}