{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,14]],"date-time":"2025-10-14T07:11:07Z","timestamp":1760425867085,"version":"3.44.0"},"publisher-location":"New York, NY, USA","reference-count":27,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,2,18]],"date-time":"2020-02-18T00:00:00Z","timestamp":1581984000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,2,18]]},"DOI":"10.1145\/3384544.3384547","type":"proceedings-article","created":{"date-parts":[[2020,5,4]],"date-time":"2020-05-04T03:58:24Z","timestamp":1588564704000},"page":"339-343","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["A Comprehensive Investigation of Universal Verification Methodology (UVM) Standard for Design Verification"],"prefix":"10.1145","author":[{"given":"Shumaila","family":"Qamar","sequence":"first","affiliation":[{"name":"Department of Computer and Software Engineering, College of E&ME, National University of Sciences and Technology (NUST), Islamabad, Pakistan"}]},{"given":"Wasi Haider","family":"Butt","sequence":"additional","affiliation":[{"name":"Department of Computer and Software Engineering, College of E&ME, National University of Sciences and Technology (NUST), Islamabad, Pakistan"}]},{"given":"Muhammad Waseem","family":"Anwar","sequence":"additional","affiliation":[{"name":"Department of Computer and Software Engineering, College of E&ME, National University of Sciences and Technology (NUST), Islamabad, Pakistan"}]},{"given":"Farooque","family":"Azam","sequence":"additional","affiliation":[{"name":"Department of Computer and Software Engineering, College of E&ME, National University of Sciences and Technology (NUST), Islamabad, Pakistan"}]},{"given":"Muhammad Qasim","family":"Khan","sequence":"additional","affiliation":[{"name":"Department of Computer and Software Engineering, College of E&ME, National University of Sciences and Technology (NUST), Islamabad, Pakistan"}]}],"member":"320","published-online":{"date-parts":[[2020,4,17]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3139540.3139544"},{"key":"e_1_3_2_1_2_1","volume-title":"On UVM Reliability in Mixed-Signal Verification IEEE 10th (LASCAS)","author":"Ramirez Gomez","year":"2019","unstructured":"Ramirez, Gomez, and E. Roa. On UVM Reliability in Mixed-Signal Verification IEEE 10th (LASCAS). 2019."},{"key":"e_1_3_2_1_3_1","first-page":"145","volume":"201","author":"Podivinsky J.","unstructured":"Podivinsky, J., et al., Functional verification based platform for evaluating fault tolerance properties. Microprocessors and Microsystems, 2017. 52: p. 145--159.","journal-title":"Microprocessors and Microsystems"},{"key":"e_1_3_2_1_4_1","first-page":"392","volume":"201","author":"Weissnegger","unstructured":"Weissnegger, et al., SHARC - Simulation and Verification of Hierarchical Embedded Microelectronic Systems. Procedia Computer Science, 2017. 109: p. 392--399.","journal-title":"Procedia Computer Science"},{"key":"e_1_3_2_1_5_1","first-page":"129","volume":"201","author":"Caba","unstructured":"Caba, et al., Testing framework for on-board verification of HLS modules using grey-box technique and FPGA overlays. Integration, 2019. 68: p. 129--138.","journal-title":"Integration"},{"key":"e_1_3_2_1_6_1","first-page":"1","volume":"201","author":"Anwar","unstructured":"Anwar, et al., Model-based design verification for embedded systems through SVOCL: an OCL extension for SystemVerilog. Design Automation for Embedded Systems, 2017. 21(1): p. 1--36.","journal-title":"Design Automation for Embedded Systems"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"Sharma L. Bhargava and V. Kumar. Automated Coverage Register Access Technology on UVM Framework for Advanced Verification. In 2018 IEEE (ISCAS).","DOI":"10.1109\/ISCAS.2018.8351413"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2019.8704549"},{"volume-title":"UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog. In 2018 28th (PATMOS)","author":"Georgoulopoulos Giannou","key":"e_1_3_2_1_9_1","unstructured":"Georgoulopoulos, Giannou, and A. Hatzopoulos. UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog. In 2018 28th (PATMOS)."},{"key":"e_1_3_2_1_10_1","volume-title":"VeriSFQ: A Semi-formal Verification Framework and Benchmark 20th Inter Symposium on Quality Electronic Design","author":"Wong","year":"2019","unstructured":"Wong, et al. VeriSFQ: A Semi-formal Verification Framework and Benchmark 20th Inter Symposium on Quality Electronic Design 2019."},{"key":"e_1_3_2_1_11_1","volume-title":"An Adaptive Closed-Loop Verification Approach in UVM-SystemC for AMS Circuits in 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI).","author":"Barros Schulz","year":"2018","unstructured":"Barros, Schulz, and D.V. Lettnin. An Adaptive Closed-Loop Verification Approach in UVM-SystemC for AMS Circuits in 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI). 2018."},{"key":"e_1_3_2_1_12_1","volume-title":"An Automated Lightweight UVM Tool. in 2018 30th International Conference on Microelectronics (ICM).","author":"Hamed","year":"2018","unstructured":"Hamed, et al. An Automated Lightweight UVM Tool. in 2018 30th International Conference on Microelectronics (ICM). 2018."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCARC.2018.8541158"},{"key":"e_1_3_2_1_14_1","volume-title":"Constructing Effective UVM Testbench for DRAM Memory Controllers. in 2018 New Generation of CAS (NGCAS)","author":"Salah Mostafa","year":"2018","unstructured":"Salah, Mostafa. Constructing Effective UVM Testbench for DRAM Memory Controllers. in 2018 New Generation of CAS (NGCAS). 2018."},{"key":"e_1_3_2_1_15_1","volume-title":"Different Reference Models for UVM Environment to Speed Up the Verification Time in 2018 19th International Workshop on Microprocessor and SOC Test and Verification (MTV)","author":"Moursi","year":"2018","unstructured":"Moursi, et al. Different Reference Models for UVM Environment to Speed Up the Verification Time in 2018 19th International Workshop on Microprocessor and SOC Test and Verification (MTV). 2018."},{"key":"e_1_3_2_1_16_1","volume-title":"A Domain-specific Language for Automated Fault Injection in SystemC Models. 25th (ICECS)","author":"Lohmann","year":"2018","unstructured":"Lohmann, et al. A Domain-specific Language for Automated Fault Injection in SystemC Models. 25th (ICECS). 2018."},{"key":"e_1_3_2_1_17_1","volume-title":"Efficient Methodology of Sampling UVM RAL during Simulation for SoC Functional Coverage in 2018 19th International Workshop on Microprocessor and SOC Test and Verification (MTV)","author":"El-Ashry Adel","year":"2018","unstructured":"El-Ashry, Adel. Efficient Methodology of Sampling UVM RAL during Simulation for SoC Functional Coverage in 2018 19th International Workshop on Microprocessor and SOC Test and Verification (MTV). 2018."},{"key":"e_1_3_2_1_18_1","volume-title":"Extending universal verification methodology with fault injection capabilities. In 2018 IEEE 9th (LASCAS)","author":"Lohmann","year":"2018","unstructured":"Lohmann, et al. Extending universal verification methodology with fault injection capabilities. In 2018 IEEE 9th (LASCAS). 2018."},{"key":"e_1_3_2_1_19_1","volume-title":"Fast Reliable Verification Methodology for RISC-V 19th International Workshop on Microprocessor and SOC Test and Verification (MTV).","author":"Munir","year":"2018","unstructured":"Munir, et al. Fast Reliable Verification Methodology for RISC-V 19th International Workshop on Microprocessor and SOC Test and Verification (MTV). 2018."},{"key":"e_1_3_2_1_20_1","volume-title":"Functional Verification of Ten Gigabytes Media Independent Interface (XGMII) Using UVM in Fourth (ICCUBEA)","author":"Chinchole Kinage","year":"2018","unstructured":"Chinchole, Kinage. Functional Verification of Ten Gigabytes Media Independent Interface (XGMII) Using UVM in Fourth (ICCUBEA) 2018."},{"key":"e_1_3_2_1_21_1","volume-title":"8th (MECO)","author":"Koh\u00fatka Stopjakov\u00e1","year":"2019","unstructured":"Koh\u00fatka Stopjakov\u00e1. A New Hardware-Accelerated Scheduler for Soft Real-Time Tasks. In 8th (MECO) 2019."},{"key":"e_1_3_2_1_22_1","volume-title":"Robust Functional Verification Framework Based in UVM Applied to an AES Encryption Module. In 2018 New Generation of CAS (NGCAS)","author":"Plasencia-Balabarca F.","year":"2018","unstructured":"Plasencia-Balabarca, F., et al. Robust Functional Verification Framework Based in UVM Applied to an AES Encryption Module. In 2018 New Generation of CAS (NGCAS). 2018."},{"volume-title":"System Level simulation framework for the ASICs development of a novel particle physics detector in 2018 14th Conference on (PRIME)","author":"Caratelli","key":"e_1_3_2_1_23_1","unstructured":"Caratelli, et al. System Level simulation framework for the ASICs development of a novel particle physics detector in 2018 14th Conference on (PRIME)"},{"key":"e_1_3_2_1_24_1","volume-title":"Darji. Transactional Test Environment for Faster and Early Verification of Digital Designs. ICCED","author":"Kakani","year":"2018","unstructured":"Kakani, and Darji. Transactional Test Environment for Faster and Early Verification of Digital Designs. ICCED 2018."},{"key":"e_1_3_2_1_25_1","volume-title":"UVM Based Testbench Architecture for Coverage Driven Functional Verification of SPI Protocol in (ICACCI)","author":"Sundari","year":"2018","unstructured":"V, B. and Sundari. UVM Based Testbench Architecture for Coverage Driven Functional Verification of SPI Protocol in (ICACCI). 2018."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2019.8741931"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2019.8742109"}],"event":{"name":"ICSCA 2020: 2020 9th International Conference on Software and Computer Applications","acronym":"ICSCA 2020","location":"Langkawi Malaysia"},"container-title":["Proceedings of the 2020 9th International Conference on Software and Computer Applications"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3384544.3384547","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3384544.3384547","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T05:19:36Z","timestamp":1755839976000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3384544.3384547"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,2,18]]},"references-count":27,"alternative-id":["10.1145\/3384544.3384547","10.1145\/3384544"],"URL":"https:\/\/doi.org\/10.1145\/3384544.3384547","relation":{},"subject":[],"published":{"date-parts":[[2020,2,18]]},"assertion":[{"value":"2020-04-17","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}