{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,16]],"date-time":"2026-04-16T01:44:23Z","timestamp":1776303863124,"version":"3.50.1"},"reference-count":37,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2020,7,16]],"date-time":"2020-07-16T00:00:00Z","timestamp":1594857600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"R8D program of MOTIE\/KEIT","award":["10077609"],"award-info":[{"award-number":["10077609"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Storage"],"published-print":{"date-parts":[[2020,8,31]]},"abstract":"<jats:p>As semiconductor technology has advanced, many storage systems have begun to use non-volatile memories as storage media. The organization and architecture of storage controllers have become more complex to meet various design requirements in terms of performance, response time, quality of service (QoS), and so on. In addition, due to the evolution of memory technology and the emergence of new applications, storage controllers employ new firmware algorithms and hardware modules. When designing storage controllers, engineers often evaluate the performance impact of using new software and hardware components using software simulators. However, this technique often yields limited evaluation accuracy because of the difficulty of modeling complex operations of components and the interactions among them. In this article, we present a reconfigurable flash storage controller design that serves as a rapid prototype. This design can be synthesized into a field-programmable gate array device and used in a realistic performance evaluation environment. We show the usefulness of our design by demonstrating the performance impact of design parameters.<\/jats:p>","DOI":"10.1145\/3385073","type":"journal-article","created":{"date-parts":[[2020,7,7]],"date-time":"2020-07-07T12:32:29Z","timestamp":1594125149000},"page":"1-35","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":64,"title":["Cosmos+ OpenSSD"],"prefix":"10.1145","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1890-2910","authenticated-orcid":false,"given":"Jaewook","family":"Kwak","sequence":"first","affiliation":[{"name":"Hanyang University, Wangsimni-ro, Seoul, Korea"}]},{"given":"Sangjin","family":"Lee","sequence":"additional","affiliation":[{"name":"Hanyang University, Wangsimni-ro, Seoul, Korea"}]},{"given":"Kibin","family":"Park","sequence":"additional","affiliation":[{"name":"Hanyang University, Wangsimni-ro, Seoul, Korea"}]},{"given":"Jinwoo","family":"Jeong","sequence":"additional","affiliation":[{"name":"Hanyang University, Wangsimni-ro, Seoul, Korea"}]},{"given":"Yong Ho","family":"Song","sequence":"additional","affiliation":[{"name":"Hanyang University, Wangsimni-ro, Seoul, Korea"}]}],"member":"320","published-online":{"date-parts":[[2020,7,16]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2015.7401757"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_3_1","unstructured":"Matias Bj\u00f8rling Javier Gonz\u00e1lez and Philippe Bonnet. 2017. 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