{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:46:02Z","timestamp":1772725562906,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":43,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,6,11]],"date-time":"2020-06-11T00:00:00Z","timestamp":1591833600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,6,11]]},"DOI":"10.1145\/3385412.3386008","type":"proceedings-article","created":{"date-parts":[[2020,6,7]],"date-time":"2020-06-07T01:40:10Z","timestamp":1591494010000},"page":"519-532","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":29,"title":["CacheQuery: learning replacement policies from hardware caches"],"prefix":"10.1145","author":[{"given":"Pepe","family":"Vila","sequence":"first","affiliation":[{"name":"IMDEA Software Institute, Spain \/ Universidad Polit\u00e9cnica de Madrid, Spain"}]},{"given":"Pierre","family":"Ganty","sequence":"additional","affiliation":[{"name":"IMDEA Software Institute, Spain"}]},{"given":"Marco","family":"Guarnieri","sequence":"additional","affiliation":[{"name":"IMDEA Software Institute, Spain"}]},{"given":"Boris","family":"K\u00f6pf","sequence":"additional","affiliation":[{"name":"Microsoft Research, UK"}]}],"member":"320","published-online":{"date-parts":[[2020,6,11]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"29th USENIX Security Symposium (USENIX Security 20)","unstructured":"2020. RELOAD+REFRESH: Abusing Cache Replacement Policies to Perform Stealthy Cache Attacks. In 29th USENIX Security Symposium (USENIX Security 20). USENIX Association, Boston, MA. https:\/\/www. usenix.org\/conference\/usenixsecurity20\/presentation\/briongos"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2013.6531080"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844475"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"Andreas Abel and Jan Reineke. 2019. nanoBench: A Low-Overhead Tool for Running Microbenchmarks on x86 Systems.","DOI":"10.1109\/ISPASS48437.2020.00014"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3297858"},{"key":"e_1_3_2_1_6_1","unstructured":"3304062"},{"key":"e_1_3_2_1_7_1","unstructured":"AbsInt. [n.d.]. AbsInt aiT Worst-Case Execution Time Analyzers. http:\/\/www.absint.com\/a3"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1016\/0890-5401(87)90052-6"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"Nathan Binkert Bradford Beckmann Gabriel Black Steven K Reinhardt Ali Saidi Arkaprava Basu Joel Hestness Derek R Hower Tushar Krishna Somayeh Sardashti et al. 2011. The gem5 simulator. ACM SIGARCH computer architecture news 39 2 (2011) 1\u20137.","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00022"},{"key":"e_1_3_2_1_11_1","volume-title":"On the Incomparability of Cache Algorithms in Terms of Timing Leakage. Logical Methods in Computer Science","author":"Ca\u00f1ones Pablo","year":"2019","unstructured":"Pablo Ca\u00f1ones, Boris K\u00f6pf, and Jan Reineke. 2019. On the Incomparability of Cache Algorithms in Terms of Timing Leakage. Logical Methods in Computer Science Volume 15, Issue 1 (2019)."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-96562-8_6"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-40667-1_15"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2756550"},{"key":"e_1_3_2_1_15_1","volume-title":"Sushi Roll: A CPU research kernel with minimal noise for cycle-by-cycle micro-architectural introspection. https: \/\/gamozolabs.github.io\/metrology\/2019\/08\/19\/sushi_roll.html","author":"Falk Brandom","year":"2019","unstructured":"Brandom Falk. 2019. Sushi Roll: A CPU research kernel with minimal noise for cycle-by-cycle micro-architectural introspection. https: \/\/gamozolabs.github.io\/metrology\/2019\/08\/19\/sushi_roll.html"},{"key":"e_1_3_2_1_16_1","volume-title":"The Cache Memory Book","author":"Handy Jim","unstructured":"Jim Handy. 1993. The Cache Memory Book. Academic Press Professional, Inc."},{"key":"e_1_3_2_1_17_1","unstructured":"Intel. 2010. How to Benchmark Code Execution Times on Intel IA-32 and IA-64 Instruction Set Architectures. https:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/ white-papers\/ia-32-ia-64-benchmark-code-execution-paper.pdf"},{"key":"e_1_3_2_1_18_1","unstructured":"Intel. 2017. Are Noisy Neighbors in Your Data Center Keeping You Up at Night. https:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/ documents\/white-papers\/intel-rdt-infrastructure-paper.pdf"},{"key":"e_1_3_2_1_19_1","unstructured":"Intel. 2018. Intel 64 and IA-32 Architectures Optimization Reference Manual. Intel. https:\/\/software.intel.com\/sites\/default\/files\/managed\/ 9e\/bc\/64-ia-32-architectures-optimization-manual.pdf"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2015.56"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-21690-4_32"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815971"},{"key":"e_1_3_2_1_23_1","volume-title":"Proceedings of the 12th International Conference on Grammatical Inference","volume":"34","author":"Khalili Ali","year":"2014","unstructured":"Ali Khalili and Armando Tacchella. 2014. Learning Nondeterministic Mealy Machines. In Proceedings of the 12th International Conference on Grammatical Inference, Vol. 34. PMLR, Kyoto, Japan, 109\u2013123."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/32.87284"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00083"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/3241189.3241280"},{"key":"e_1_3_2_1_27_1","volume-title":"Hayes","author":"Malamy Adam","year":"1992","unstructured":"Adam Malamy, Rajiv Patel N., and Norma M. Hayes. 1992. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature. https:\/\/patents.google.com\/patent\/ US5353425A\/en US5353425A."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-26362-5_3"},{"key":"e_1_3_2_1_31_1","volume-title":"DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks. In 25th USENIX Security Symposium (USENIX Security 16)","author":"Pessl Peter","year":"2016","unstructured":"Peter Pessl, Daniel Gruss, Cl\u00e9mentine Maurice, Michael Schwarz, and Stefan Mangard. 2016. DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks. In 25th USENIX Security Symposium (USENIX Security 16). USENIX Association, 565\u2013581. https:\/\/www.usenix.org\/ conference\/usenixsecurity16\/technical-sessions\/presentation\/pessl"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1150019"},{"key":"e_1_3_2_1_34_1","unstructured":"1136501"},{"key":"e_1_3_2_1_35_1","volume-title":"Learning Cache Replacement Policies using Register Automata. Master\u2018s thesis","author":"Rueda Guillem","unstructured":"Guillem Rueda. 2013. Learning Cache Replacement Policies using Register Automata. Master\u2018s thesis, Uppsala University, Department of Information Technology."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-10672-9_3"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-21455-4_8"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-009-9049-y"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/2967606"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","unstructured":"Pepe Vila. 2019. CacheQuery\u2019s Github Repository. 5281\/zenodo.3759108 10.5281\/zenodo.3759108","DOI":"10.5281\/zenodo.3759108"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","unstructured":"Pepe Vila. 2019. Polca\u2019s Github Repository. zenodo.3759110 10.5281\/zenodo.3759110","DOI":"10.5281\/zenodo.3759110"},{"key":"e_1_3_2_1_42_1","volume-title":"Cache-Query: Learning Replacement Policies from Hardware Caches. CoRR abs\/1912.09770","author":"Vila Pepe","year":"2019","unstructured":"Pepe Vila, Pierre Ganty, Marco Guarnieri, and Boris K\u00f6pf. 2019. Cache-Query: Learning Replacement Policies from Hardware Caches. CoRR abs\/1912.09770 (2019). http:\/\/arxiv.org\/abs\/1912.09770"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/sp.2019.00042"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/1347375.1347389"},{"key":"e_1_3_2_1_45_1","unstructured":"Henry Wong. 2013. Intel Ivy Bridge Cache Replacement Policy. http: \/\/blog.stuffedcow.net\/2013\/01\/ivb-cache-replacement\/"}],"event":{"name":"PLDI '20: 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation","location":"London UK","acronym":"PLDI '20","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages"]},"container-title":["Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3385412.3386008","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3385412.3386008","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:38:49Z","timestamp":1750199929000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3385412.3386008"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,6,11]]},"references-count":43,"alternative-id":["10.1145\/3385412.3386008","10.1145\/3385412"],"URL":"https:\/\/doi.org\/10.1145\/3385412.3386008","relation":{},"subject":[],"published":{"date-parts":[[2020,6,11]]},"assertion":[{"value":"2020-06-11","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}