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MIT press."},{"key":"e_1_3_2_1_70_1","unstructured":"George A Reis Jonathan Chang Neil Vachharajani Shubhendu S Mukherjee Ram Rangan and David I August. 2005."},{"key":"e_1_3_2_1_71_1","volume-title":"32nd International Symposium on Computer Architecture (ISCA\u201905)","author":"Design","unstructured":"Design and evaluation of hybrid fault-detection systems. In 32nd International Symposium on Computer Architecture (ISCA\u201905). IEEE, 148\u2013159."},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"crossref","unstructured":"Muhammad Shafique Siddharth Garg J\u00f6rg Henkel and Diana Marculescu. 2014. The EDA Challenges in the Dark Silicon Era: Temperature Reliability and Variability Perspectives. In DAC \u201914.","DOI":"10.1145\/2593069.2593229"},{"key":"e_1_3_2_1_74_1","volume-title":"RTL and Guide, Modeling.","year":"2001","unstructured":"Synopsys. 2001. Compiler, Design and User, RTL and Guide, Modeling. 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