{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T19:20:35Z","timestamp":1762024835621,"version":"build-2065373602"},"publisher-location":"New York, NY, USA","reference-count":14,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,9,7]],"date-time":"2020-09-07T00:00:00Z","timestamp":1599436800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Natural Science Foundation of China","award":["61877010","11501114"],"award-info":[{"award-number":["61877010","11501114"]}]},{"name":"Fujian Natural Science Funds","award":["2019J01243"],"award-info":[{"award-number":["2019J01243"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,9,7]]},"DOI":"10.1145\/3386263.3406902","type":"proceedings-article","created":{"date-parts":[[2020,9,4]],"date-time":"2020-09-04T21:34:20Z","timestamp":1599255260000},"page":"107-112","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique"],"prefix":"10.1145","author":[{"given":"Zhen","family":"Zhuang","sequence":"first","affiliation":[{"name":"Fuzhou University, Fuzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Genggeng","family":"Liu","sequence":"additional","affiliation":[{"name":"Fuzhou University, Fuzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xing","family":"Huang","sequence":"additional","affiliation":[{"name":"Fuzhou University, Fuzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaotao","family":"Jia","sequence":"additional","affiliation":[{"name":"Beihang University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wen-Hao","family":"Liu","sequence":"additional","affiliation":[{"name":"Block Implementation, ICD, Cadence Design Systems, Austin, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenzhong","family":"Guo","sequence":"additional","affiliation":[{"name":"Fuzhou University, Fuzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,9,7]]},"reference":[{"key":"e_1_3_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-014-9155-4"},{"key":"e_1_3_2_2_2_1","doi-asserted-by":"crossref","unstructured":"A. Ling and J. Anderson \"The role of FPGAs in deep learning \" in Proceedings of International Symposium on Field-Programmable Gate Arrays pp. 3--3 2017.  A. Ling and J. Anderson \"The role of FPGAs in deep learning \" in Proceedings of International Symposium on Field-Programmable Gate Arrays pp. 3--3 2017.","DOI":"10.1145\/3020078.3030013"},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"crossref","unstructured":"G. A. Constantinides \"FPGAs in the cloud \" in Proceedings of International Symposium on Field-Programmable Gate Arrays pp. 167--167 2017.  G. A. Constantinides \"FPGAs in the cloud \" in Proceedings of International Symposium on Field-Programmable Gate Arrays pp. 167--167 2017.","DOI":"10.1145\/3020078.3030014"},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.663540"},{"key":"e_1_3_2_2_5_1","unstructured":"J. Babb R. Tessier and A. Agarwal \"Virtual wires: Overcoming pin limitations in FPGA-based logic emulators \" in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines pp. 142--151 1993.  J. Babb R. Tessier and A. Agarwal \"Virtual wires: Overcoming pin limitations in FPGA-based logic emulators \" in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines pp. 142--151 1993."},{"key":"e_1_3_2_2_6_1","doi-asserted-by":"crossref","unstructured":"G. L. Zhang B. Li M. Hashimoto and U. Schlichtmann \"VirtualSync: Timing optimization by synchronizing logic waves with sequential and combinational components as delay units \" in Proceedings of Design Automation Conference pp. 26:1--26:6 2018.  G. L. Zhang B. Li M. Hashimoto and U. Schlichtmann \"VirtualSync: Timing optimization by synchronizing logic waves with sequential and combinational components as delay units \" in Proceedings of Design Automation Conference pp. 26:1--26:6 2018.","DOI":"10.1109\/DAC.2018.8465936"},{"key":"e_1_3_2_2_7_1","doi-asserted-by":"crossref","unstructured":"W. N. N. Hung and R. Sun \"Challenges in large FPGA-based logic emulation systems \" in Proceedings of International Symposium on Physical Design pp. 26--33 2018.  W. N. N. Hung and R. Sun \"Challenges in large FPGA-based logic emulation systems \" in Proceedings of International Symposium on Physical Design pp. 26--33 2018.","DOI":"10.1145\/3177540.3177542"},{"issue":"6","key":"e_1_3_2_2_8_1","first-page":"609","article-title":"Logic emulation with virtual wires","volume":"16","author":"Babb J.","year":"1997","journal-title":"IEEE TCAD"},{"key":"e_1_3_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjtsldm.3.81"},{"key":"e_1_3_2_2_10_1","doi-asserted-by":"crossref","unstructured":"M. Inagi Y. Takashima and Y. Nakamura \"Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems \" in Proceedings of International Conference on Field Programmable Logic and Applications pp. 212--217 2009.  M. Inagi Y. Takashima and Y. Nakamura \"Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems \" in Proceedings of International Conference on Field Programmable Logic and Applications pp. 212--217 2009.","DOI":"10.1109\/FPL.2009.5272309"},{"key":"e_1_3_2_2_11_1","first-page":"12","article-title":"Inter-FPGA routing for partially time-multiplexing inter-FPGA signals on multi-FPGA systems with various topologies","volume":"98","author":"Inagi M.","year":"2015","journal-title":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"},{"key":"e_1_3_2_2_12_1","doi-asserted-by":"crossref","unstructured":"S.-C. Chen R. Sun and Y.-W. Chang \"Simultaneous partitioning and signals grouping for time division multiplexing in 2.5D FPGA-based systems \" in Proceedings of International Conference on Computer-Aided Design pp. 4:1--4:7 2018.  S.-C. Chen R. Sun and Y.-W. Chang \"Simultaneous partitioning and signals grouping for time division multiplexing in 2.5D FPGA-based systems \" in Proceedings of International Conference on Computer-Aided Design pp. 4:1--4:7 2018.","DOI":"10.1145\/3240765.3240847"},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1016\/0020-0190(88)90066-X"},{"key":"e_1_3_2_2_14_1","unstructured":"2019 ICCAD CAD Contest. Available: http:\/\/iccad-contest.org\/2019\/.  2019 ICCAD CAD Contest. Available: http:\/\/iccad-contest.org\/2019\/."}],"event":{"name":"GLSVLSI '20: Great Lakes Symposium on VLSI 2020","acronym":"GLSVLSI '20","location":"Virtual Event China"},"container-title":["Proceedings of the 2020 on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3406902","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3386263.3406902","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:13:13Z","timestamp":1750201993000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3406902"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,7]]},"references-count":14,"alternative-id":["10.1145\/3386263.3406902","10.1145\/3386263"],"URL":"https:\/\/doi.org\/10.1145\/3386263.3406902","relation":{},"subject":[],"published":{"date-parts":[[2020,9,7]]},"assertion":[{"value":"2020-09-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}