{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:27:00Z","timestamp":1750220820996,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,9,7]],"date-time":"2020-09-07T00:00:00Z","timestamp":1599436800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100011103","name":"European Commission","doi-asserted-by":"publisher","award":["863337"],"award-info":[{"award-number":["863337"]}],"id":[{"id":"10.13039\/100011103","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001381","name":"National Research Foundation Singapore","doi-asserted-by":"publisher","award":["A1892b0026"],"award-info":[{"award-number":["A1892b0026"]}],"id":[{"id":"10.13039\/501100001381","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100011199","name":"European Research Council","doi-asserted-by":"publisher","award":["725657"],"award-info":[{"award-number":["725657"]}],"id":[{"id":"10.13039\/100011199","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100006512","name":"Nanyang Technological University","doi-asserted-by":"publisher","award":["M4082035"],"award-info":[{"award-number":["M4082035"]}],"id":[{"id":"10.13039\/501100006512","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,9,7]]},"DOI":"10.1145\/3386263.3406923","type":"proceedings-article","created":{"date-parts":[[2020,9,4]],"date-time":"2020-09-04T21:34:23Z","timestamp":1599255263000},"page":"513-518","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology"],"prefix":"10.1145","author":[{"given":"Halima","family":"Najibi","sequence":"first","affiliation":[{"name":"EPFL, Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexandre","family":"Levisse","sequence":"additional","affiliation":[{"name":"EPFL, Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marina","family":"Zapater","sequence":"additional","affiliation":[{"name":"EPFL & University of Applied Sciences Western Switzerland (HEIG-VD, HES-SO), Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohamed M.","family":"Sabry Aly","sequence":"additional","affiliation":[{"name":"Nanyang Technological University (NTU), Singapore, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Atienza","sequence":"additional","affiliation":[{"name":"EPFL, Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,9,7]]},"reference":[{"key":"e_1_3_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242496"},{"key":"e_1_3_2_2_2_1","volume-title":"IEEE International Electron Devices Meeting (IEDM)","author":"Auth C.","year":"2014","unstructured":"C. Auth A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 \u00b5m2SRAM cell size . IEEE International Electron Devices Meeting (IEDM) , 2014 . C. Auth et al. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 \u00b5m2SRAM cell size. IEEE International Electron Devices Meeting (IEDM), 2014."},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268472"},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838334"},{"key":"e_1_3_2_2_5_1","unstructured":"IEEE 2016 International Roadmap for Devices and Systems (IRDS). https:\/\/irds.ieee.org\/images\/files\/pdf\/2016_MM.pdf.  IEEE 2016 International Roadmap for Devices and Systems (IRDS). https:\/\/irds.ieee.org\/images\/files\/pdf\/2016_MM.pdf."},{"key":"e_1_3_2_2_6_1","unstructured":"IRDS 2018. https:\/\/irds.ieee.org\/images\/files\/pdf\/2018\/2018IRDS_MM.pdf.  IRDS 2018. https:\/\/irds.ieee.org\/images\/files\/pdf\/2018\/2018IRDS_MM.pdf."},{"key":"e_1_3_2_2_7_1","volume-title":"Design-Process-Technology Co-optimization for Manufacturability","author":"Ban Y.","year":"2017","unstructured":"Y. Ban IR-drop analysis for validating power grids and standard cell architectures in sub-10nm node designs . Design-Process-Technology Co-optimization for Manufacturability , 2017 . Y. Ban et al. IR-drop analysis for validating power grids and standard cell architectures in sub-10nm node designs. Design-Process-Technology Co-optimization for Manufacturability, 2017."},{"key":"e_1_3_2_2_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001401"},{"key":"e_1_3_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.7873\/DATE2014.147"},{"key":"e_1_3_2_2_10_1","volume":"201","author":"Andreev A.","unstructured":"A. Andreev PowerCool: Simulation of Cooling and Powering of 3D MPSoCs with Integrated Flow Cell Arrays. IEEE Transactions on Computers (TC) , 201 8. A. Andreev et al. PowerCool: Simulation of Cooling and Powering of 3D MPSoCs with Integrated Flow Cell Arrays. IEEE Transactions on Computers (TC), 2018.","journal-title":"IEEE Transactions on Computers (TC)"},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2019.8824895"},{"key":"e_1_3_2_2_12_1","doi-asserted-by":"publisher","DOI":"10.7873\/DATE2014.290"},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ITHERM.2018.8419545"},{"key":"e_1_3_2_2_14_1","volume-title":"ISSCC","author":"Fluhr E.","year":"2014","unstructured":"E. Fluhr : a 12 core server-class processor in 22nm SOI with 7.6Tb\/s off-chip bandwidth . ISSCC , 2014 . E. Fluhr et al. POWER8: a 12 core server-class processor in 22nm SOI with 7.6Tb\/s off-chip bandwidth. ISSCC, 2014."},{"key":"e_1_3_2_2_15_1","volume-title":"ISCA","author":"Jouppi N.","year":"2017","unstructured":"N. Jouppi In-datacenter performance analysis of a tensor processing unit . ISCA , 2017 . N. Jouppi et al. In-datacenter performance analysis of a tensor processing unit. ISCA, 2017."},{"key":"e_1_3_2_2_16_1","volume-title":"DOSSA Workshop","author":"Tang T.","year":"2018","unstructured":"T. Tang : A power area timing modeling framework for machine learning accelerators . DOSSA Workshop , 2018 . T. Tang et al. MLPAT: A power area timing modeling framework for machine learning accelerators. DOSSA Workshop, 2018."},{"key":"e_1_3_2_2_17_1","volume":"201","author":"Christen D.","unstructured":"D. Christen Energy Efficient Heat Sink Design: Natural Versus Forced Convection Cooling. IEEE Transactions on Power Electronics , 201 7. D. Christen et al. Energy Efficient Heat Sink Design: Natural Versus Forced Convection Cooling. IEEE Transactions on Power Electronics, 2017.","journal-title":"IEEE Transactions on Power Electronics"},{"key":"e_1_3_2_2_18_1","volume-title":"Symposium on VLSI Technology","author":"Wu S.","year":"2009","unstructured":"S. Wu . A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual\/tripe gate oxide process . Symposium on VLSI Technology , 2009 . S. Wu. A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual\/tripe gate oxide process. Symposium on VLSI Technology, 2009."},{"key":"e_1_3_2_2_19_1","volume-title":"DAC","author":"Sinha S.","year":"2012","unstructured":"S. Sinha FinFET design with Predictive Technology Models . DAC , 2012 . S. Sinha et al. Exploring sub-20nm FinFET design with Predictive Technology Models. DAC, 2012."},{"key":"e_1_3_2_2_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2010.39"},{"key":"e_1_3_2_2_21_1","volume":"201","author":"Iranfar A.","unstructured":"A. Iranfar Machine Learning-Based Quality-Aware Power and Thermal Management of Multistream HEVC Encoding on Multicore Servers. IEEE Transactions on Parallel and Distributed Systems , 201 8. A. Iranfar et al. Machine Learning-Based Quality-Aware Power and Thermal Management of Multistream HEVC Encoding on Multicore Servers. IEEE Transactions on Parallel and Distributed Systems, 2018.","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"e_1_3_2_2_22_1","volume-title":"3D-ICE: a compact thermal model for early-stage design of liquid-cooled ICs. TC","author":"Sridhar A.","year":"2014","unstructured":"A. Sridhar 3D-ICE: a compact thermal model for early-stage design of liquid-cooled ICs. TC , 2014 . A. Sridhar et al. 3D-ICE: a compact thermal model for early-stage design of liquid-cooled ICs. TC, 2014."}],"event":{"name":"GLSVLSI '20: Great Lakes Symposium on VLSI 2020","acronym":"GLSVLSI '20","location":"Virtual Event China"},"container-title":["Proceedings of the 2020 on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3406923","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3386263.3406923","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:13:13Z","timestamp":1750201993000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3406923"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,7]]},"references-count":22,"alternative-id":["10.1145\/3386263.3406923","10.1145\/3386263"],"URL":"https:\/\/doi.org\/10.1145\/3386263.3406923","relation":{},"subject":[],"published":{"date-parts":[[2020,9,7]]},"assertion":[{"value":"2020-09-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}