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Huang et al., \"Variability-and reliability-aware design for 16\/14nm and beyond technology,\" in 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2017, pp. 12.4.1--12.4.4."},{"key":"e_1_3_2_2_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-019-2643-5"},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2289874"},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2520658"},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2463083"},{"key":"e_1_3_2_2_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2501310"},{"key":"e_1_3_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691098"},{"key":"e_1_3_2_2_8_1","article-title":"Circuit Reliability Comparison between Stochastic Computing and Binary Computing","author":"Zhang Z.","unstructured":"Z. Zhang , \" Circuit Reliability Comparison between Stochastic Computing and Binary Computing ,\" in IEEE Transactions on Circuits and Systems II: Express Briefs , doi: 10.1109\/TCSII.2020.2993273. 10.1109\/TCSII.2020.2993273 Z. Zhang et al., \"Circuit Reliability Comparison between Stochastic Computing and Binary Computing,\" in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109\/TCSII.2020.2993273.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"e_1_3_2_2_9_1","first-page":"1","volume-title":"Avignon","author":"Han J.","year":"2013","unstructured":"J. Han : An emerging paradigm for energy-efficient design,\" 2013 18th IEEE European Test Symposium (ETS) , Avignon , 2013 , pp. 1 -- 6 . J. Han et al., \"Approximate computing: An emerging paradigm for energy-efficient design,\" 2013 18th IEEE European Test Symposium (ETS), Avignon, 2013, pp. 1--6."},{"key":"e_1_3_2_2_10_1","first-page":"1","article-title":"Invited - Cross-layer approximate computing: from logic to architectures,\" in Proceedings of the 53rd Annual Design Automation Conference on - DAC '16, Austin","author":"Shafique M.","year":"2016","unstructured":"M. Shafique , \" Invited - Cross-layer approximate computing: from logic to architectures,\" in Proceedings of the 53rd Annual Design Automation Conference on - DAC '16, Austin , Texas , 2016 , pp. 1 -- 6 . M. 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Amrouch et al., \"Towards Aging-Induced Approximations,\" in Proceedings of the 54th Annual Design Automation Conference 2017 on - DAC '17, Austin, TX, USA, 2017, pp. 1--6."},{"key":"e_1_3_2_2_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2217962"},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2217962"},{"key":"e_1_3_2_2_14_1","first-page":"1","volume-title":"A low latency generic accuracy configurable adder,\" 2015 52nd ACM\/EDAC\/IEEE Design Automation Conference (DAC)","author":"Shafique M.","year":"2015","unstructured":"M. Shafique , \" A low latency generic accuracy configurable adder,\" 2015 52nd ACM\/EDAC\/IEEE Design Automation Conference (DAC) , San Francisco, CA , 2015 , pp. 1 -- 6 . doi: 10.1145\/2744769.2744778 10.1145\/2744769.2744778 M. Shafique et al., \"A low latency generic accuracy configurable adder,\" 2015 52nd ACM\/EDAC\/IEEE Design Automation Conference (DAC), San Francisco, CA, 2015, pp. 1--6. doi: 10.1145\/2744769.2744778"},{"key":"e_1_3_2_2_15_1","first-page":"346","volume-title":"Chennai","author":"Kulkarni P.","year":"2011","unstructured":"P. Kulkarni Power with an Underdesigned Multiplier Architecture,\" 2011 24th Internatioal Conference on VLSI Design , Chennai , 2011 , pp. 346 -- 351 . doi: 10.1109\/VLSID.2011.51 10.1109\/VLSID.2011.51 P. Kulkarni et al., \"Trading Accuracy for Power with an Underdesigned Multiplier Architecture,\" 2011 24th Internatioal Conference on VLSI Design, Chennai, 2011, pp. 346--351. doi: 10.1109\/VLSID.2011.51"},{"key":"e_1_3_2_2_16_1","first-page":"1","article-title":"A Novel Heuristic Search Method for Two-level Approximate Logic Synthesis","author":"Su S.","year":"2019","unstructured":"S. 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