{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,14]],"date-time":"2026-01-14T04:42:39Z","timestamp":1768365759059,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,9,7]],"date-time":"2020-09-07T00:00:00Z","timestamp":1599436800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Key-Area Research and Development Program of GuangDong Province","award":["2019B010142001"],"award-info":[{"award-number":["2019B010142001"]}]},{"name":"High-level University Fund","award":["G02236002"],"award-info":[{"award-number":["G02236002"]}]},{"name":"University Key Laboratory of Advanced Wireless Communications of Guangdong Province","award":["2018KSYS005"],"award-info":[{"award-number":["2018KSYS005"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,9,7]]},"DOI":"10.1145\/3386263.3406941","type":"proceedings-article","created":{"date-parts":[[2020,9,4]],"date-time":"2020-09-04T21:34:20Z","timestamp":1599255260000},"page":"493-498","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Analog Circuit Implementation of Neurons with Multiply-Accumulate and ReLU Functions"],"prefix":"10.1145","author":[{"given":"Yucong","family":"Huang","sequence":"first","affiliation":[{"name":"Southern University of Science and Technology, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhitao","family":"Yang","sequence":"additional","affiliation":[{"name":"Southern University of Science and Technology, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianghan","family":"Zhu","sequence":"additional","affiliation":[{"name":"Southern University of Science and Technology, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Terry Tao","family":"Ye","sequence":"additional","affiliation":[{"name":"Southern University of Science and Technology, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,9,7]]},"reference":[{"key":"e_1_3_2_2_1_1","volume-title":"et al","author":"Schuman C.D.","year":"2017","unstructured":"Schuman , C.D. et al . 2017 . A Survey of Neuromorphic Computing and Neural Networks in Hardware . arXiv. (2017), 1--88. DOI: https:\/\/doi.org\/10.1016\/j.neucom.2010.03.021. 10.1016\/j.neucom.2010.03.021 Schuman, C.D. et al. 2017. A Survey of Neuromorphic Computing and Neural Networks in Hardware. arXiv. (2017), 1--88. DOI: https:\/\/doi.org\/10.1016\/j.neucom.2010.03.021."},{"key":"e_1_3_2_2_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2601069"},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF02478259"},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2014.10.015"},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1080\/03772063.2017.1351315"},{"key":"e_1_3_2_2_6_1","first-page":"1045","article-title":"\u00b1 0.75V Four Quadrant Analog Multiplier In Current. 2018 15th International Multi-Conference on Systems","volume":"1","author":"Aloui I.","year":"2018","unstructured":"Aloui , I. 2018 . \u00b1 0.75V Four Quadrant Analog Multiplier In Current. 2018 15th International Multi-Conference on Systems , Signals & Devices (SSD). 1 (2018), 1045 -- 1050 . Aloui, I. et al. 2018. \u00b1 0.75V Four Quadrant Analog Multiplier In Current. 2018 15th International Multi-Conference on Systems, Signals & Devices (SSD). 1 (2018), 1045--1050.","journal-title":"Signals & Devices (SSD)."},{"key":"#cr-split#-e_1_3_2_2_7_1.1","doi-asserted-by":"crossref","unstructured":"Satansup J. and Tangsrirat W. 2018. 1.5-V CMOS Current Multiplier \/ Divider. 2018 International Journal of Electrical and Computer Engineering (IJECE). 8 3 (2018) 1478--1487. DOI: https:\/\/doi.org\/10.11591\/ijece.v8i3.pp1478--1487. 10.11591\/ijece.v8i3.pp1478--1487","DOI":"10.11591\/ijece.v8i3.pp1478-1487"},{"key":"#cr-split#-e_1_3_2_2_7_1.2","doi-asserted-by":"crossref","unstructured":"Satansup J. and Tangsrirat W. 2018. 1.5-V CMOS Current Multiplier \/ Divider. 2018 International Journal of Electrical and Computer Engineering (IJECE). 8 3 (2018) 1478--1487. DOI: https:\/\/doi.org\/10.11591\/ijece.v8i3.pp1478--1487.","DOI":"10.11591\/ijece.v8i3.pp1478-1487"},{"key":"e_1_3_2_2_8_1","volume-title":"et al","author":"Aloui I.","year":"2017","unstructured":"Aloui , I. et al . 2017 . A CMOS current mode four quadrant analog multiplier free from mobility reduction. AEU - International Journal of Electronics and Communications . 82, (2017), 119--126. DOI: https:\/\/doi.org\/10.1016\/j.aeue.2017.08.006. 10.1016\/j.aeue.2017.08.006 Aloui, I. et al. 2017. A CMOS current mode four quadrant analog multiplier free from mobility reduction. AEU - International Journal of Electronics and Communications. 82, (2017), 119--126. DOI: https:\/\/doi.org\/10.1016\/j.aeue.2017.08.006."},{"key":"e_1_3_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.1007\/s13369-017-2968-2"},{"key":"e_1_3_2_2_10_1","doi-asserted-by":"publisher","DOI":"10.1049\/el:20072528"},{"key":"e_1_3_2_2_11_1","first-page":"5","volume-title":"18th International Conference on Sciences and Techniques of Automatic control & computer engineering. 4","author":"Aloui I.","year":"2017","unstructured":"Aloui , I. et al. 2017. Low-Voltage low-Power Four-Quadrant Analog Multiplier In Current-Mode . 18th International Conference on Sciences and Techniques of Automatic control & computer engineering. 4 , 5 ( 2017 ), 163--167. Aloui, I. et al. 2017. Low-Voltage low-Power Four-Quadrant Analog Multiplier In Current-Mode. 18th International Conference on Sciences and Techniques of Automatic control & computer engineering. 4, 5 (2017), 163--167."},{"key":"e_1_3_2_2_12_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2008.06.002"},{"key":"e_1_3_2_2_13_1","volume-title":"et al","author":"Priyanka P.","year":"2019","unstructured":"Priyanka , P. et al . 2019 . CMOS Implementation of Rectfied Linear Activation Function. VLSI Design and Test . (2019), 121--129. Priyanka, P. et al. 2019. CMOS Implementation of Rectfied Linear Activation Function. VLSI Design and Test. (2019), 121--129."},{"key":"e_1_3_2_2_14_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.4896668"},{"key":"e_1_3_2_2_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2157739"}],"event":{"name":"GLSVLSI '20: Great Lakes Symposium on VLSI 2020","location":"Virtual Event China","acronym":"GLSVLSI '20"},"container-title":["Proceedings of the 2020 on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3406941","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3386263.3406941","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:38:25Z","timestamp":1750199905000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3406941"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,7]]},"references-count":16,"alternative-id":["10.1145\/3386263.3406941","10.1145\/3386263"],"URL":"https:\/\/doi.org\/10.1145\/3386263.3406941","relation":{},"subject":[],"published":{"date-parts":[[2020,9,7]]},"assertion":[{"value":"2020-09-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}