{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:25:32Z","timestamp":1750220732727,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,9,7]],"date-time":"2020-09-07T00:00:00Z","timestamp":1599436800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,9,7]]},"DOI":"10.1145\/3386263.3406951","type":"proceedings-article","created":{"date-parts":[[2020,9,4]],"date-time":"2020-09-04T21:34:23Z","timestamp":1599255263000},"page":"487-492","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors"],"prefix":"10.1145","author":[{"given":"Chirag","family":"Joshi","sequence":"first","affiliation":[{"name":"College Of Engineering Pune, Pune, India"}]},{"given":"Palash","family":"Das","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology, Guwahati, Guwahati, India"}]},{"given":"Ashwini","family":"Kulkarni","sequence":"additional","affiliation":[{"name":"College Of Engineering Pune, Pune, India"}]},{"given":"Hemangee K.","family":"Kapoor","sequence":"additional","affiliation":[{"name":"Indian Institute of Technogy, Guwahati, Guwahati, India"}]}],"member":"320","published-online":{"date-parts":[[2020,9,7]]},"reference":[{"key":"e_1_3_2_2_1_1","doi-asserted-by":"crossref","unstructured":"Alessandro Bardine et al. 2007 a. Analysis of static and dynamic energy consumption in nuca caches: Initial results. In MEDEA. ACM 105--112.  Alessandro Bardine et al. 2007 a. Analysis of static and dynamic energy consumption in nuca caches: Initial results. In MEDEA. ACM 105--112.","DOI":"10.1145\/1327171.1327184"},{"key":"e_1_3_2_2_2_1","doi-asserted-by":"crossref","unstructured":"Alankar V Umdekar etal 2018. Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. In VLSID. IEEE.  Alankar V Umdekar et al. 2018. Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. In VLSID. IEEE.","DOI":"10.1109\/VLSID.2018.33"},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"crossref","unstructured":"Christian Bienia et al. 2008a. The PARSEC benchmark suite: Characterization and architectural implications. In PACT. ACM 72--81.  Christian Bienia et al. 2008a. The PARSEC benchmark suite: Characterization and architectural implications. In PACT. ACM 72--81.","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_2_4_1","first-page":"13","article-title":"Spin-transfer torque magnetic random access memory (STT-MRAM)","volume":"9","author":"Dmytro Apalkov","year":"2013","unstructured":"Dmytro Apalkov et al. 2013 a. Spin-transfer torque magnetic random access memory (STT-MRAM) . JETC , Vol. 9 , 2 (2013), 13 . Dmytro Apalkov et al. 2013a. Spin-transfer torque magnetic random access memory (STT-MRAM). JETC, Vol. 9, 2 (2013), 13.","journal-title":"JETC"},{"key":"e_1_3_2_2_5_1","first-page":"13","article-title":"Performance\/thermal-aware design of 3D-stacked L2 caches for CMPs","volume":"17","author":"Guangyu Sun","year":"2012","unstructured":"Guangyu Sun et al. 2012 a. Performance\/thermal-aware design of 3D-stacked L2 caches for CMPs . TODAES , Vol. 17 , 2 (2012), 13 . Guangyu Sun et al. 2012a. Performance\/thermal-aware design of 3D-stacked L2 caches for CMPs. TODAES, Vol. 17, 2 (2012), 13.","journal-title":"TODAES"},{"key":"e_1_3_2_2_6_1","doi-asserted-by":"crossref","unstructured":"Hadi Esmaeilzadeh et al. 2011a. Dark silicon and the end of multicore scaling. In ISCA. IEEE 365--376.  Hadi Esmaeilzadeh et al. 2011a. Dark silicon and the end of multicore scaling. In ISCA. IEEE 365--376.","DOI":"10.1145\/2024723.2000108"},{"key":"e_1_3_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2361150"},{"key":"e_1_3_2_2_8_1","first-page":"592","article-title":"b. Thermal management of on-chip caches through power density minimization","volume":"15","author":"Ku Ja Chun","year":"2007","unstructured":"Ja Chun Ku 2007 b. Thermal management of on-chip caches through power density minimization . TVLSI , Vol. 15 , 5 (2007), 592 -- 604 . Ja Chun Ku et al. 2007 b. Thermal management of on-chip caches through power density minimization. TVLSI, Vol. 15, 5 (2007), 592--604.","journal-title":"TVLSI"},{"key":"e_1_3_2_2_9_1","first-page":"13","article-title":"Recent thermal management techniques for microprocessors","volume":"44","author":"Joonho Kong","year":"2012","unstructured":"Joonho Kong et al. 2012 b. Recent thermal management techniques for microprocessors . CSUR , Vol. 44 , 3 (2012), 13 . Joonho Kong et al. 2012b. Recent thermal management techniques for microprocessors. CSUR, Vol. 44, 3 (2012), 13.","journal-title":"CSUR"},{"key":"e_1_3_2_2_10_1","volume-title":"WAP: Improving non-volatile cache lifetime by reducing inter-and intra-set write variations","author":"Jue Wang","year":"2013","unstructured":"Jue Wang et al. 2013 b. i 2 WAP: Improving non-volatile cache lifetime by reducing inter-and intra-set write variations . In HPCA. IEEE , 234--245. Jue Wang et al. 2013b. i 2 WAP: Improving non-volatile cache lifetime by reducing inter-and intra-set write variations. In HPCA. IEEE, 234--245."},{"key":"e_1_3_2_2_11_1","first-page":"589","article-title":"TSIC","volume":"3746","author":"Kyriakos Stavrou","year":"2005","unstructured":"Kyriakos Stavrou et al. 2005 . TSIC : Thermal Scheduling Simulator for Chip Multiprocessors , Vol. 3746. 589 -- 599 . https:\/\/doi.org\/10.1007\/11573036_56 10.1007\/11573036_56 Kyriakos Stavrou et al. 2005. TSIC: Thermal Scheduling Simulator for Chip Multiprocessors, Vol. 3746. 589--599. https:\/\/doi.org\/10.1007\/11573036_56","journal-title":"Thermal Scheduling Simulator for Chip Multiprocessors"},{"key":"e_1_3_2_2_12_1","first-page":"941","article-title":"Chip temperature optimization for dark silicon many-core systems","volume":"37","author":"Mengquan Li","year":"2017","unstructured":"Mengquan Li et al. 2017 . Chip temperature optimization for dark silicon many-core systems . TCAD , Vol. 37 , 5 (2017), 941 -- 953 . Mengquan Li et al. 2017. Chip temperature optimization for dark silicon many-core systems. TCAD, Vol. 37, 5 (2017), 941--953.","journal-title":"TCAD"},{"key":"e_1_3_2_2_13_1","first-page":"2","article-title":"Analysis of SRAM and eDRAM cache memories under spatial temperature variations","volume":"29","author":"Mesut Meterelliyoz","year":"2009","unstructured":"Mesut Meterelliyoz et al. 2009 a. Analysis of SRAM and eDRAM cache memories under spatial temperature variations . IEEE TCAD , Vol. 29 , 1 (2009), 2 -- 13 . Mesut Meterelliyoz et al. 2009a. Analysis of SRAM and eDRAM cache memories under spatial temperature variations. IEEE TCAD, Vol. 29, 1 (2009), 2--13.","journal-title":"IEEE TCAD"},{"key":"e_1_3_2_2_14_1","doi-asserted-by":"crossref","unstructured":"Muhammad Shafique et al. 2014a. Dark silicon as a challenge for hardware\/software co-design: Invited special session paper. In CODES. ACM 13.  Muhammad Shafique et al. 2014a. Dark silicon as a challenge for hardware\/software co-design: Invited special session paper. In CODES. ACM 13.","DOI":"10.1145\/2656075.2661645"},{"key":"e_1_3_2_2_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2016.2633408"},{"key":"e_1_3_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_2_17_1","doi-asserted-by":"crossref","unstructured":"Raid Ayoub et al. 2010. Performance and energy efficient cache migrationapproach for thermal management in embedded systems. In GLSVLSI. ACM 365--368.  Raid Ayoub et al. 2010. Performance and energy efficient cache migrationapproach for thermal management in embedded systems. In GLSVLSI. ACM 365--368.","DOI":"10.1145\/1785481.1785565"},{"key":"e_1_3_2_2_18_1","unstructured":"Runjie Zhang et al. 2015b. Hotspot 6.0: Validation acceleration and extension. University of Virginia Tech. Rep (2015).  Runjie Zhang et al. 2015b. Hotspot 6.0: Validation acceleration and extension. University of Virginia Tech. Rep (2015)."},{"key":"e_1_3_2_2_19_1","article-title":"Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design","volume":"24","author":"Shounak Chakraborty","year":"2019","unstructured":"Shounak Chakraborty et al. 2019 . Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design . ACM Trans. Des. Autom. Electron. Syst. , Vol. 24 , 5 (2019). Shounak Chakraborty et al. 2019. Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design. ACM Trans. Des. Autom. Electron. Syst., Vol. 24, 5 (2019).","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"e_1_3_2_2_20_1","doi-asserted-by":"crossref","unstructured":"S. Li et al. 2009b. McPAT: An integrated power area and timing modeling framework for multicore and manycore architectures. In MICRO. 469--480.  S. Li et al. 2009b. McPAT: An integrated power area and timing modeling framework for multicore and manycore architectures. In MICRO. 469--480.","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_2_21_1","doi-asserted-by":"crossref","unstructured":"Sparsh Mittal et al. 2014b. LastingNVCache: A technique for improving the lifetime of non-volatile caches. In ISVLSI. IEEE 534--540.  Sparsh Mittal et al. 2014b. LastingNVCache: A technique for improving the lifetime of non-volatile caches. In ISVLSI. IEEE 534--540.","DOI":"10.1109\/ISVLSI.2014.69"},{"key":"e_1_3_2_2_22_1","doi-asserted-by":"crossref","unstructured":"Sobhan Niknam et al. 2015c. Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age. In ReCoSoC. IEEE 1--8.  Sobhan Niknam et al. 2015c. Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age. In ReCoSoC. IEEE 1--8.","DOI":"10.1109\/ReCoSoC.2015.7238085"},{"key":"e_1_3_2_2_23_1","unstructured":"Shyamkumar Thoziyoor et al. 2008b. CACTI 5.1. Technical Report. Technical Report HP Labs.  Shyamkumar Thoziyoor et al. 2008b. CACTI 5.1. Technical Report. Technical Report HP Labs."},{"key":"e_1_3_2_2_24_1","doi-asserted-by":"crossref","unstructured":"V. Hanumaiah et al. 2009c. Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. In ICCAD. 310--313.  V. Hanumaiah et al. 2009c. Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. In ICCAD. 310--313.","DOI":"10.1145\/1687399.1687458"},{"key":"e_1_3_2_2_25_1","first-page":"32","article-title":"A survey on cache tuning from a power\/energy perspective","volume":"45","author":"Wei Zang","year":"2013","unstructured":"Wei Zang et al. 2013 c. A survey on cache tuning from a power\/energy perspective . CSUR , Vol. 45 , 3 (2013), 32 . Wei Zang et al. 2013c. A survey on cache tuning from a power\/energy perspective. CSUR, Vol. 45, 3 (2013), 32.","journal-title":"CSUR"},{"key":"e_1_3_2_2_26_1","first-page":"994","article-title":"NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory","volume":"31","author":"Xiangyu Dong","year":"2012","unstructured":"Xiangyu Dong et al. 2012 c. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory . TCAD , Vol. 31 (2012), 994 -- 1007 . Xiangyu Dong et al. 2012c. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. TCAD, Vol. 31 (2012), 994--1007.","journal-title":"TCAD"},{"key":"e_1_3_2_2_27_1","volume-title":"SIGARCH","volume":"37","author":"Xiaoxia","unstructured":"Xiaoxia Wu et al. 2009 d. Hybrid cache architecture with disparate memory technologies . In SIGARCH , Vol. 37 . ACM, 34--45. Xiaoxia Wu et al. 2009 d. Hybrid cache architecture with disparate memory technologies. In SIGARCH, Vol. 37. ACM, 34--45."},{"volume-title":"2012 d. Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design","author":"Chen Yu-Ting","key":"e_1_3_2_2_28_1","unstructured":"Yu-Ting Chen 2012 d. Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design . In DATE. EDA Consortium , 45--50. Yu-Ting Chen et al. 2012 d. Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. In DATE. EDA Consortium, 45--50."}],"event":{"name":"GLSVLSI '20: Great Lakes Symposium on VLSI 2020","acronym":"GLSVLSI '20","location":"Virtual Event China"},"container-title":["Proceedings of the 2020 on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3406951","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3386263.3406951","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:38:25Z","timestamp":1750199905000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3406951"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,7]]},"references-count":28,"alternative-id":["10.1145\/3386263.3406951","10.1145\/3386263"],"URL":"https:\/\/doi.org\/10.1145\/3386263.3406951","relation":{},"subject":[],"published":{"date-parts":[[2020,9,7]]},"assertion":[{"value":"2020-09-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}