{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,16]],"date-time":"2026-04-16T01:44:14Z","timestamp":1776303854176,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":40,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,9,7]],"date-time":"2020-09-07T00:00:00Z","timestamp":1599436800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,9,7]]},"DOI":"10.1145\/3386263.3406956","type":"proceedings-article","created":{"date-parts":[[2020,9,4]],"date-time":"2020-09-04T21:34:23Z","timestamp":1599255263000},"page":"283-290","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices"],"prefix":"10.1145","author":[{"given":"Cong","family":"Hao","sequence":"first","affiliation":[{"name":"University of Illinois at Urbana-Champaign & IBM-Illinois Center for Cognitive Computing Systems Research (C3SR), Urbana-Champaign, IL, USA"}]},{"given":"Yao","family":"Chen","sequence":"additional","affiliation":[{"name":"Advanced Digital Sciences Center, Singapore, Singapore, Singapore"}]},{"given":"Xiaofan","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign & IBM-Illinois Center for Cognitive Computing Systems Research (C3SR), Urbana-Champaign, IL, USA"}]},{"given":"Yuhong","family":"Li","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign & IBM-Illinois Center for Cognitive Computing Systems Research (C3SR), Urbana-Champaign, IL, USA"}]},{"given":"Jinjun","family":"Xiong","sequence":"additional","affiliation":[{"name":"IBM T. J. Watson Research Center & IBM-Illinois Center for Cognitive Computing Systems Research (C3SR), New York, NY, USA"}]},{"given":"Wen-mei","family":"Hwu","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign & IBM-Illinois Center for Cognitive Computing Systems Research (C3SR), Urbana-Champaign, IL, USA"}]},{"given":"Deming","family":"Chen","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign & IBM-Illinois Center for Cognitive Computing Systems Research (C3SR), Urbana-Champaign, IL, USA"}]}],"member":"320","published-online":{"date-parts":[[2020,9,7]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Proceedings of the International Conference on Learning Representations (ICLR)","author":"Han","year":"2019","unstructured":"Han Cai et al. Proxylessnas: Direct neural architecture search on target task and hardware . In Proceedings of the International Conference on Learning Representations (ICLR) , 2019 . Han Cai et al. Proxylessnas: Direct neural architecture search on target task and hardware. In Proceedings of the International Conference on Learning Representations (ICLR), 2019."},{"key":"e_1_3_2_1_2_1","volume-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR)","author":"Mingxing","year":"2019","unstructured":"Mingxing Tan et al. Mnasnet: Platform-aware neural architecture search for mobile . In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR) , 2019 . Mingxing Tan et al. Mnasnet: Platform-aware neural architecture search for mobile. In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2019."},{"key":"e_1_3_2_1_3_1","volume-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR)","author":"Bichen","year":"2019","unstructured":"Bichen Wu et al. Fbnet: Hardware-aware efficient convnet design via differentiable neural architecture search . In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR) , 2019 . Bichen Wu et al. Fbnet: Hardware-aware efficient convnet design via differentiable neural architecture search. In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2019."},{"key":"e_1_3_2_1_4_1","volume-title":"NVIDIA Jetson AGX Xavier delivers 32 teraops for new era ofAI in robotics. NVIDIA Accelerated Computing| Parallel For all","author":"Franklin Dustin","year":"2018","unstructured":"Dustin Franklin . NVIDIA Jetson AGX Xavier delivers 32 teraops for new era ofAI in robotics. NVIDIA Accelerated Computing| Parallel For all , 2018 . Dustin Franklin. NVIDIA Jetson AGX Xavier delivers 32 teraops for new era ofAI in robotics. NVIDIA Accelerated Computing| Parallel For all, 2018."},{"key":"e_1_3_2_1_5_1","volume-title":"Proceedings of International Symposium on Computer Architecture (ISCA),2017","author":"Norman","unstructured":"Norman P Jouppi et al. In-data center performance analysis of a tensor processing unit . In Proceedings of International Symposium on Computer Architecture (ISCA),2017 . Norman P Jouppi et al. In-data center performance analysis of a tensor processing unit. In Proceedings of International Symposium on Computer Architecture (ISCA),2017."},{"key":"e_1_3_2_1_6_1","volume-title":"IEEE International Solid-State Circuits Conference (ISSCC)","author":"Yu-Hsin","year":"2016","unstructured":"Yu-Hsin Chen et al. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks . In IEEE International Solid-State Circuits Conference (ISSCC) , 2016 . Yu-Hsin Chen et al. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. In IEEE International Solid-State Circuits Conference (ISSCC), 2016."},{"key":"e_1_3_2_1_7_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","author":"Xiaofan","year":"2017","unstructured":"Xiaofan Zhang et al. High-performance video content recognition with long-term recurrent convolutional network for FPGA . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) , 2017 . Xiaofan Zhang et al. High-performance video content recognition with long-term recurrent convolutional network for FPGA. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2017."},{"key":"e_1_3_2_1_8_1","volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC)","author":"Qin","year":"2019","unstructured":"Qin Li et al. Implementing neural machine translation with bi-directional gru and attention mechanism on FPGAs using HLS . In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC) , 2019 . Qin Li et al. Implementing neural machine translation with bi-directional gru and attention mechanism on FPGAs using HLS. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2019."},{"key":"e_1_3_2_1_9_1","volume-title":"Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA)","author":"Song","year":"2017","unstructured":"Song Han et al. ESE: Efficient speech recognition engine with sparse lstm on FPGA . In Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA) , 2017 . Song Han et al. ESE: Efficient speech recognition engine with sparse lstm on FPGA. In Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA), 2017."},{"key":"e_1_3_2_1_10_1","volume-title":"Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI),2018","author":"Chuanhao","unstructured":"Chuanhao Zhuge et al. Face recognition with hybrid efficient convolution algorithms on FPGAs . In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI),2018 . Chuanhao Zhuge et al. Face recognition with hybrid efficient convolution algorithms on FPGAs. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI),2018."},{"key":"e_1_3_2_1_11_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","author":"Junsong","year":"2018","unstructured":"Junsong Wang et al. Design flow of accelerating hybrid extremely low bit-width neural network in embedded FPGA . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) , 2018 . Junsong Wang et al. Design flow of accelerating hybrid extremely low bit-width neural network in embedded FPGA. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2018."},{"key":"e_1_3_2_1_12_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Xiaofan","year":"2018","unstructured":"Xiaofan Zhang et al. DNNBuilder: an automated tool for building high-performance DNN hardware accelerators for FPGAs . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD) , 2018 . Xiaofan Zhang et al. DNNBuilder: an automated tool for building high-performance DNN hardware accelerators for FPGAs. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), 2018."},{"key":"e_1_3_2_1_13_1","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference (DAC)","author":"Hanchen","year":"2020","unstructured":"Hanchen Ye et al. HybridDNN: A framework for high-performance hybrid dnn accelerator design and implementation . In Proceedings of the ACM\/IEEE Design Automation Conference (DAC) , 2020 . Hanchen Ye et al. HybridDNN: A framework for high-performance hybrid dnn accelerator design and implementation. In Proceedings of the ACM\/IEEE Design Automation Conference (DAC), 2020."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2018.8564956"},{"key":"e_1_3_2_1_15_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Cong","year":"2019","unstructured":"Cong Hao et al. NAIS: Neural architecture and implementation search and its applications in autonomous driving . Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD) , 2019 . Cong Hao et al. NAIS: Neural architecture and implementation search and its applications in autonomous driving. Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), 2019."},{"key":"e_1_3_2_1_16_1","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference (DAC)","author":"Cong","year":"2019","unstructured":"Cong Hao et al. FPGA\/DNN co-design: An efficient design methodology for1ot intelligence on the edge . In Proceedings of the ACM\/IEEE Design Automation Conference (DAC) , 2019 . Cong Hao et al. FPGA\/DNN co-design: An efficient design methodology for1ot intelligence on the edge. In Proceedings of the ACM\/IEEE Design Automation Conference (DAC), 2019."},{"key":"e_1_3_2_1_17_1","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference (DAC)","author":"Weiwen","year":"2019","unstructured":"Weiwen Jiang et al. Accuracy vs. efficiency: Achieving both through fpga-implementation aware neural architecture search . In Proceedings of the ACM\/IEEE Design Automation Conference (DAC) , 2019 . Weiwen Jiang et al. Accuracy vs. efficiency: Achieving both through fpga-implementation aware neural architecture search. In Proceedings of the ACM\/IEEE Design Automation Conference (DAC), 2019."},{"key":"e_1_3_2_1_18_1","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference (DAC)","author":"Yuhong","year":"2020","unstructured":"Yuhong Li et al. EDD: Efficient differentiable dnn architecture and implementation co-search for embedded AI solutions . Proceedings of the ACM\/IEEE Design Automation Conference (DAC) , 2020 . Yuhong Li et al. EDD: Efficient differentiable dnn architecture and implementation co-search for embedded AI solutions. Proceedings of the ACM\/IEEE Design Automation Conference (DAC), 2020."},{"key":"e_1_3_2_1_19_1","volume-title":"Proceedings of Machine Learning and Systems (MLSys)","author":"Xiaofan","year":"2020","unstructured":"Xiaofan Zhang et al. SkyNet: a hardware-efficient method for object detection and tracking on embedded systems . In Proceedings of Machine Learning and Systems (MLSys) , 2020 . Xiaofan Zhang et al. SkyNet: a hardware-efficient method for object detection and tracking on embedded systems. In Proceedings of Machine Learning and Systems (MLSys), 2020."},{"key":"e_1_3_2_1_20_1","volume-title":"Co-exploration of neural architectures and heterogeneous asic accelerator designs targeting multiple tasks.Proceedings of the ACM\/IEEE Design Automation Conference (DAC)","author":"Lei Yang","year":"2020","unstructured":"Lei Yang et al. Co-exploration of neural architectures and heterogeneous asic accelerator designs targeting multiple tasks.Proceedings of the ACM\/IEEE Design Automation Conference (DAC) , 2020 . Lei Yang et al. Co-exploration of neural architectures and heterogeneous asic accelerator designs targeting multiple tasks.Proceedings of the ACM\/IEEE Design Automation Conference (DAC), 2020."},{"key":"e_1_3_2_1_21_1","volume-title":"Proceedings of the International Conference on Learning Representations (ICLR)","author":"Hanxiao","year":"2019","unstructured":"Hanxiao Liu et al. Darts: Differentiable architecture search . In Proceedings of the International Conference on Learning Representations (ICLR) , 2019 . Hanxiao Liu et al. Darts: Differentiable architecture search. In Proceedings of the International Conference on Learning Representations (ICLR), 2019."},{"key":"e_1_3_2_1_22_1","volume-title":"Joint European Conference on Machine Learning and Knowledge Discovery in Databases","author":"Dimitrios","year":"2019","unstructured":"Dimitrios Stamoulis et al. Single-path nas: Designing hardware-efficient convnets in less than 4 hours . In Joint European Conference on Machine Learning and Knowledge Discovery in Databases , 2019 . Dimitrios Stamoulis et al. Single-path nas: Designing hardware-efficient convnets in less than 4 hours. In Joint European Conference on Machine Learning and Knowledge Discovery in Databases, 2019."},{"key":"e_1_3_2_1_23_1","volume-title":"Bit fusion: Bit-level dynamically composable architecture for accelerating deep neural networks","author":"Hardik Sharma","year":"2018","unstructured":"Hardik Sharma et al. Bit fusion: Bit-level dynamically composable architecture for accelerating deep neural networks . In ISCA. IEEE , 2018 . Hardik Sharma et al. Bit fusion: Bit-level dynamically composable architecture for accelerating deep neural networks. In ISCA. IEEE, 2018."},{"key":"e_1_3_2_1_24_1","volume-title":"Loom: Exploiting weight and activation precisions to accelerate convolutional neural networks","author":"Sayeh Sharify","year":"2018","unstructured":"Sayeh Sharify et al. Loom: Exploiting weight and activation precisions to accelerate convolutional neural networks . In DAC. IEEE , 2018 . Sayeh Sharify et al. Loom: Exploiting weight and activation precisions to accelerate convolutional neural networks. In DAC. IEEE, 2018."},{"key":"e_1_3_2_1_25_1","volume":"201","author":"Xiaowei Xu","unstructured":"Xiaowei Xu et al. DAC-SDC low power object detection challenge for UAV applications. IEEE Transactions on Pattern Analysis and Machine Intelligence , 201 9. Xiaowei Xu et al. DAC-SDC low power object detection challenge for UAV applications. IEEE Transactions on Pattern Analysis and Machine Intelligence,2019.","journal-title":"IEEE Transactions on Pattern Analysis and Machine Intelligence"},{"key":"e_1_3_2_1_26_1","first-page":"2020","volume":"201","author":"Kara Kaan","unstructured":"Kaan Kara , Ce Zhang , and Gustavo Alonso . DAC-SDC'18 2nd place winner in FPGA track. https:\/\/github.com\/fpgasystems\/spoo NN , 201 8. Accessed: 2020 - 2002 --28. Kaan Kara, Ce Zhang, and Gustavo Alonso. DAC-SDC'18 2nd place winner in FPGA track. https:\/\/github.com\/fpgasystems\/spooNN, 2018. Accessed: 2020-02--28.","journal-title":"NN"},{"key":"e_1_3_2_1_27_1","volume-title":"DAC-SDC'19 3rd place winner in FPGA track,2019","author":"Kara Kaan","unstructured":"Kaan Kara and Gustavo Alonso . DAC-SDC'19 3rd place winner in FPGA track,2019 . Kaan Kara and Gustavo Alonso. DAC-SDC'19 3rd place winner in FPGA track,2019."},{"key":"e_1_3_2_1_28_1","volume-title":"DAC-SDC'19 2nd place winner in GPU track","author":"Feng Xiong","year":"2019","unstructured":"Feng Xiong et al. DAC-SDC'19 2nd place winner in GPU track , 2019 . Feng Xiong et al. DAC-SDC'19 2nd place winner in GPU track, 2019."},{"key":"e_1_3_2_1_29_1","volume-title":"DAC-SDC'19 3rd place winner in GPU track","author":"Jianing Deng","year":"2019","unstructured":"Jianing Deng et al. DAC-SDC'19 3rd place winner in GPU track , 2019 . Jianing Deng et al. DAC-SDC'19 3rd place winner in GPU track, 2019."},{"key":"e_1_3_2_1_30_1","volume-title":"DAC-SDC'18 1st place winner in GPU track.https:\/\/github.com\/lvhao7896\/DAC2018","author":"Hao Lu","year":"2018","unstructured":"Hao Lu et al. DAC-SDC'18 1st place winner in GPU track.https:\/\/github.com\/lvhao7896\/DAC2018 , 2018 . Accessed : 2020-02--28. Hao Lu et al. DAC-SDC'18 1st place winner in GPU track.https:\/\/github.com\/lvhao7896\/DAC2018, 2018. Accessed: 2020-02--28."},{"key":"e_1_3_2_1_31_1","volume-title":"DAC-SDC'18 3rd place winner in GPU track. https:\/\/github.com\/xiaoyuuuuu\/dac-hdc-2018-object-detection-in-Jetson-TX2","author":"Chuanqi Zang","year":"2018","unstructured":"Chuanqi Zang et al. DAC-SDC'18 3rd place winner in GPU track. https:\/\/github.com\/xiaoyuuuuu\/dac-hdc-2018-object-detection-in-Jetson-TX2 , 2018 . Accessed : 2020-02--28. Chuanqi Zang et al. DAC-SDC'18 3rd place winner in GPU track. https:\/\/github.com\/xiaoyuuuuu\/dac-hdc-2018-object-detection-in-Jetson-TX2, 2018. Accessed: 2020-02--28."},{"key":"e_1_3_2_1_32_1","volume-title":"DAC-SDC'19 2nd place winner in FPGA track","author":"Boran Zhao","year":"2019","unstructured":"Boran Zhao et al. DAC-SDC'19 2nd place winner in FPGA track , 2019 . Boran Zhao et al. DAC-SDC'19 2nd place winner in FPGA track, 2019."},{"key":"e_1_3_2_1_33_1","volume-title":"DAC-SDC'18 1st place winner in FPGA track. https:\/\/github.com\/hirayaku\/DAC2018-TGIIF","author":"Shulin Zeng","year":"2018","unstructured":"Shulin Zeng et al. DAC-SDC'18 1st place winner in FPGA track. https:\/\/github.com\/hirayaku\/DAC2018-TGIIF , 2018 . Accessed : 2020-02--28. Shulin Zeng et al. DAC-SDC'18 1st place winner in FPGA track. https:\/\/github.com\/hirayaku\/DAC2018-TGIIF, 2018. Accessed: 2020-02--28."},{"key":"e_1_3_2_1_34_1","volume-title":"DAC-SDC'18 3rd place winner in FPGA track.https:\/\/github.com\/onioncc\/iSmartDNN","author":"Cong Hao","year":"2018","unstructured":"Cong Hao et al. DAC-SDC'18 3rd place winner in FPGA track.https:\/\/github.com\/onioncc\/iSmartDNN , 2018 . Accessed : 2020-02--28. Cong Hao et al. DAC-SDC'18 3rd place winner in FPGA track.https:\/\/github.com\/onioncc\/iSmartDNN, 2018. Accessed: 2020-02--28."},{"key":"e_1_3_2_1_35_1","unstructured":"Xilinx. ChaiDNN. https:\/\/github.com\/Xilinx\/CHaiDNN.  Xilinx. ChaiDNN. https:\/\/github.com\/Xilinx\/CHaiDNN."},{"key":"e_1_3_2_1_36_1","volume-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition(CVPR)","author":"Mark","year":"2018","unstructured":"Mark Sandler et al. MobileNetV2: Inverted residuals and linear bottlenecks . In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition(CVPR) , 2018 . Mark Sandler et al. MobileNetV2: Inverted residuals and linear bottlenecks. In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition(CVPR), 2018."},{"key":"e_1_3_2_1_37_1","volume-title":"Proceedings of the European Conference on Computer Vision(ECCV)","author":"Ningning","year":"2018","unstructured":"Ningning Ma et al. ShuffleNet V2: Practical guidelines for efficient CNN architecture design . In Proceedings of the European Conference on Computer Vision(ECCV) , 2018 . Ningning Ma et al. ShuffleNet V2: Practical guidelines for efficient CNN architecture design. In Proceedings of the European Conference on Computer Vision(ECCV), 2018."},{"key":"e_1_3_2_1_38_1","volume-title":"Got-10k: A large high-diversity benchmark for generic object tracking in the wild","author":"Lianghua Huang","year":"2019","unstructured":"Lianghua Huang et al. Got-10k: A large high-diversity benchmark for generic object tracking in the wild .IEEE Transactions on Pattern Analysis and Machine Intelligence , 2019 . Lianghua Huang et al. Got-10k: A large high-diversity benchmark for generic object tracking in the wild.IEEE Transactions on Pattern Analysis and Machine Intelligence, 2019."},{"key":"e_1_3_2_1_39_1","volume-title":"Proceedings of the IEEE conference on computer vision and pattern recognition (CVPR)","author":"Bo","year":"2019","unstructured":"Bo Li et al. Siamrpn++: Evolution of siamese visual tracking with very deep networks . In Proceedings of the IEEE conference on computer vision and pattern recognition (CVPR) , 2019 . Bo Li et al. Siamrpn++: Evolution of siamese visual tracking with very deep networks. In Proceedings of the IEEE conference on computer vision and pattern recognition (CVPR), 2019."},{"key":"e_1_3_2_1_40_1","volume-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR)","author":"Qiang","year":"2019","unstructured":"Qiang Wang et al. Fast online object tracking and segmentation: A unifying approach . In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR) , 2019 . Qiang Wang et al. Fast online object tracking and segmentation: A unifying approach. In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2019."}],"event":{"name":"GLSVLSI '20: Great Lakes Symposium on VLSI 2020","location":"Virtual Event China","acronym":"GLSVLSI '20"},"container-title":["Proceedings of the 2020 on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3406956","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3386263.3406956","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:38:25Z","timestamp":1750199905000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3406956"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,7]]},"references-count":40,"alternative-id":["10.1145\/3386263.3406956","10.1145\/3386263"],"URL":"https:\/\/doi.org\/10.1145\/3386263.3406956","relation":{},"subject":[],"published":{"date-parts":[[2020,9,7]]},"assertion":[{"value":"2020-09-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}