{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,23]],"date-time":"2026-01-23T08:58:45Z","timestamp":1769158725045,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":36,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,9,7]],"date-time":"2020-09-07T00:00:00Z","timestamp":1599436800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,9,7]]},"DOI":"10.1145\/3386263.3407580","type":"proceedings-article","created":{"date-parts":[[2020,9,4]],"date-time":"2020-09-04T21:34:23Z","timestamp":1599255263000},"page":"39-44","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["Modeling and Benchmarking Computing-in-Memory for Design Space Exploration"],"prefix":"10.1145","author":[{"given":"Dayane","family":"Reis","sequence":"first","affiliation":[{"name":"University of Notre Dame, Notre Dame, IN, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Di","family":"Gao","sequence":"additional","affiliation":[{"name":"Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shaahin","family":"Angizi","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xunzhao","family":"Yin","sequence":"additional","affiliation":[{"name":"Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Deliang","family":"Fan","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Niemier","sequence":"additional","affiliation":[{"name":"University of Notre Dame, Notre Dame, IN, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cheng","family":"Zhuo","sequence":"additional","affiliation":[{"name":"Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"X. Sharon","family":"Hu","sequence":"additional","affiliation":[{"name":"University of Notre Dame, Notre Dame, IN, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,9,7]]},"reference":[{"issue":"314","key":"e_1_3_2_2_1_1","first-page":"347","article-title":"Data-intensive applications, challenges, techniques and technologies: A survey on big data","volume":"275","author":"Chen C. P.","year":"2014","journal-title":"Information Sciences"},{"key":"e_1_3_2_2_2_1","doi-asserted-by":"crossref","unstructured":"W. A. Wulf etal Hitting the memory wall: implications of the obvious. ACM SIGARCH computer architecture news 23(1):20--24 1995.  W. A. Wulf et al. Hitting the memory wall: implications of the obvious. ACM SIGARCH computer architecture news 23(1):20--24 1995.","DOI":"10.1145\/216585.216588"},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.21"},{"issue":"4","key":"e_1_3_2_2_4_1","first-page":"1009","article-title":"A 28 nm Configurable Memory (TCAM\/BCAM\/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory","volume":"51","author":"Jeloka S.","year":"2016","journal-title":"JSSC"},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2014.6855225"},{"key":"e_1_3_2_2_6_1","first-page":"127","volume-title":"Automation Test in Europe Conference Exhibition (DATE)","author":"Reis D.","year":"2020"},{"issue":"4","key":"e_1_3_2_2_7_1","first-page":"635","article-title":"Logic Design Within Memristive Memories Using Memristor-Aided loGIC (MAGIC)","volume":"15","author":"Talati N.","year":"2016","journal-title":"TNANO"},{"key":"e_1_3_2_2_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2445741"},{"key":"e_1_3_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715270"},{"key":"e_1_3_2_2_10_1","unstructured":"S. Jain etal Computing in Memory With Spin-Transfer Torque Magnetic RAM. TVLSI PP(99):1--14 2017.  S. Jain et al. Computing in Memory With Spin-Transfer Torque Magnetic RAM. TVLSI PP(99):1--14 2017."},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2017.8009200"},{"key":"e_1_3_2_2_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/3218603.3218640"},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3299874.3319450"},{"key":"e_1_3_2_2_14_1","first-page":"1590","volume-title":"DATE","author":"Zhu Y.","year":"2020"},{"key":"e_1_3_2_2_15_1","first-page":"1751","volume-title":"DATE","author":"Zhang S.","year":"2019"},{"key":"e_1_3_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2019.00044"},{"key":"e_1_3_2_2_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2966484"},{"key":"e_1_3_2_2_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"e_1_3_2_2_19_1","volume-title":"DATE","author":"Poremba M.","year":"2015"},{"key":"e_1_3_2_2_20_1","first-page":"383","volume-title":"2018 ISCA","author":"Eckert C.","year":"2018"},{"key":"e_1_3_2_2_21_1","first-page":"273","volume-title":"2017 MICRO","author":"Seshadri V.","year":"2017"},{"key":"e_1_3_2_2_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858419"},{"key":"e_1_3_2_2_23_1","volume-title":"ISSCC","author":"Patterson D.","year":"1997"},{"key":"e_1_3_2_2_24_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2015.2409732"},{"key":"e_1_3_2_2_25_1","doi-asserted-by":"crossref","unstructured":"D. Patterson etal A case for intelligent RAM. IEEE Micro 17(2) 1997.  D. Patterson et al. A case for intelligent RAM. IEEE Micro 17(2) 1997.","DOI":"10.1109\/40.592312"},{"key":"e_1_3_2_2_26_1","first-page":"1","volume-title":"Benchmarking and Metrics for Emerging Memory. In 2017 IEEE International Memory Workshop (IMW)","author":"Prall K.","year":"2017"},{"key":"e_1_3_2_2_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2019.2930284"},{"key":"e_1_3_2_2_28_1","first-page":"33","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE)","author":"Chen K.","year":"2012"},{"key":"e_1_3_2_2_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317764"},{"key":"e_1_3_2_2_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147172"},{"issue":"6","key":"e_1_3_2_2_31_1","first-page":"805","article-title":"Physics-based circuit-compatible spice model for ferroelectric transistors","volume":"37","author":"Aziz A.","year":"2016","journal-title":"IEEE Electron Device Lett."},{"key":"e_1_3_2_2_32_1","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2804"},{"key":"e_1_3_2_2_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_2_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838493"},{"key":"e_1_3_2_2_35_1","first-page":"T166","volume-title":"2013 Symposium on VLSI Technology","author":"Hsu C.-W.","year":"2013"},{"key":"e_1_3_2_2_36_1","doi-asserted-by":"crossref","unstructured":"C.-H. Cheng etal Low-leakage-current dram-like memory using a one-transistor ferroelectric mosfet with a hf-based gate dielectric. IEEE electron device letters 35:138--140 2013.  C.-H. Cheng et al. Low-leakage-current dram-like memory using a one-transistor ferroelectric mosfet with a hf-based gate dielectric. IEEE electron device letters 35:138--140 2013.","DOI":"10.1109\/LED.2013.2290117"}],"event":{"name":"GLSVLSI '20: Great Lakes Symposium on VLSI 2020","location":"Virtual Event China","acronym":"GLSVLSI '20"},"container-title":["Proceedings of the 2020 on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3407580","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3386263.3407580","content-type":"text\/html","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3386263.3407580","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3386263.3407580","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:38:25Z","timestamp":1750199905000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3407580"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,7]]},"references-count":36,"alternative-id":["10.1145\/3386263.3407580","10.1145\/3386263"],"URL":"https:\/\/doi.org\/10.1145\/3386263.3407580","relation":{},"subject":[],"published":{"date-parts":[[2020,9,7]]},"assertion":[{"value":"2020-09-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}