{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,8]],"date-time":"2025-11-08T17:54:32Z","timestamp":1762624472663,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":55,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,9,7]],"date-time":"2020-09-07T00:00:00Z","timestamp":1599436800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Natural Science Foundation of China","award":["61872251"],"award-info":[{"award-number":["61872251"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,9,7]]},"DOI":"10.1145\/3386263.3407596","type":"proceedings-article","created":{"date-parts":[[2020,9,4]],"date-time":"2020-09-04T21:34:23Z","timestamp":1599255263000},"page":"369-374","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems"],"prefix":"10.1145","author":[{"given":"Keni","family":"Qiu","sequence":"first","affiliation":[{"name":"Capital Normal University, Beijing, China"}]},{"given":"Mengying","family":"Zhao","sequence":"additional","affiliation":[{"name":"Shandong University, Qingdao, China"}]},{"given":"Zhenge","family":"Jia","sequence":"additional","affiliation":[{"name":"University of Pittsburgh, Pittsburgh, PA, USA"}]},{"given":"Jingtong","family":"Hu","sequence":"additional","affiliation":[{"name":"University of Pittsburgh, Pittsburgh, PA, USA"}]},{"given":"Chun Jason","family":"Xue","sequence":"additional","affiliation":[{"name":"City University of Hong Kong, Hong Kong, China"}]},{"given":"Kaisheng","family":"Ma","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Xueqing","family":"Li","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Yongpan","family":"Liu","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Vijaykrishnan","family":"Narayanan","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, State College, PA, USA"}]}],"member":"320","published-online":{"date-parts":[[2020,9,7]]},"reference":[{"key":"e_1_3_2_2_1_1","unstructured":"https:\/\/www.ubuntupit.com\/top-20-emerging-iot-trends-that-will-shape-your-future-soon\/.  https:\/\/www.ubuntupit.com\/top-20-emerging-iot-trends-that-will-shape-your-future-soon\/."},{"key":"e_1_3_2_2_2_1","first-page":"012","article-title":"Energy harvesting piezoelectric wind speed sensor","volume":"1407","author":"Mayue Shi A. S. H.","year":"2019","unstructured":"A. S. H. Mayue Shi , Eric M Yeatman , \" Energy harvesting piezoelectric wind speed sensor ,\" Journal of Physics: Conference Series , vol. 1407 , pp. 012 -- 044 , Nov 2019 . A. S. H. Mayue Shi, Eric M Yeatman, \"Energy harvesting piezoelectric wind speed sensor,\" Journal of Physics: Conference Series, vol. 1407, pp. 012--044, Nov 2019.","journal-title":"Journal of Physics: Conference Series"},{"key":"e_1_3_2_2_3_1","unstructured":"https:\/\/assistcenter.org\/inertial-energy-harvesting\/.  https:\/\/assistcenter.org\/inertial-energy-harvesting\/."},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2019.2908610"},{"key":"e_1_3_2_2_5_1","first-page":"95","volume-title":"A simple and efficient solar energy harvesting for wireless sensor node,\" in ICRCICN'16","author":"Mangrulkar M.","unstructured":"M. Mangrulkar and S. G. Akojwar , \" A simple and efficient solar energy harvesting for wireless sensor node,\" in ICRCICN'16 , pp. 95 -- 99 . M. Mangrulkar and S. G. Akojwar, \"A simple and efficient solar energy harvesting for wireless sensor node,\" in ICRCICN'16, pp. 95--99."},{"volume-title":"Self-powered multiparameter health sensor,\" IEEE journal of biomedical and health informatics","author":"Tobola A.","key":"e_1_3_2_2_6_1","unstructured":"A. Tobola , H. Leutheuser , M. Pollak , P. Spies , C. Hofmann , C. Weigand , B. M. Eskofier , and G. Fischer , \" Self-powered multiparameter health sensor,\" IEEE journal of biomedical and health informatics , vol. 22 , no. 1, pp. 15--22, 2018. A. Tobola, H. Leutheuser, M. Pollak, P. Spies, C. Hofmann, C. Weigand, B. M. Eskofier, and G. Fischer, \"Self-powered multiparameter health sensor,\" IEEE journal of biomedical and health informatics, vol. 22, no. 1, pp. 15--22, 2018."},{"key":"e_1_3_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2013.2264931"},{"volume-title":"Self-powered zigbee wireless sensor nodes for railway condition monitoring,\" IEEE TITS'18","author":"Gao M.","key":"e_1_3_2_2_8_1","unstructured":"M. Gao , P. Wang , Y. Wang , and L. Yao , \" Self-powered zigbee wireless sensor nodes for railway condition monitoring,\" IEEE TITS'18 , vol. 19 , no. 3, pp. 900--909. M. Gao, P. Wang, Y. Wang, and L. Yao, \"Self-powered zigbee wireless sensor nodes for railway condition monitoring,\" IEEE TITS'18, vol. 19, no. 3, pp. 900--909."},{"key":"e_1_3_2_2_9_1","first-page":"316","volume-title":"Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units,\" in ASP-DAC'15","author":"Xie M.","unstructured":"M. Xie , C. Pan , J. Hu , C. Yang , and Y. Chen , \" Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units,\" in ASP-DAC'15 , pp. 316 -- 321 . M. Xie, C. Pan, J. Hu, C. Yang, and Y. Chen, \"Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units,\" in ASP-DAC'15, pp. 316--321."},{"key":"e_1_3_2_2_10_1","unstructured":"J. Yue R. Liu W. Sun Z. Yuan Z. Wang Y. Tu Y. Chen A. Ren Y. Wang M. Chang X. Li H. Yang and Y. Liu \"7.5 a 65nm 0.39-to-140.3tops\/w 1-to-12b unified neural network processor using block-circulant-enabled transpose-domain acceleration with 8.1 \u00d7 higher tops\/mm2and 6t hbst-tram-based 2d data-reuse architecture \" in ISSCC'19 pp. 138--140.  J. Yue R. Liu W. Sun Z. Yuan Z. Wang Y. Tu Y. Chen A. Ren Y. Wang M. Chang X. Li H. Yang and Y. Liu \"7.5 a 65nm 0.39-to-140.3tops\/w 1-to-12b unified neural network processor using block-circulant-enabled transpose-domain acceleration with 8.1 \u00d7 higher tops\/mm2and 6t hbst-tram-based 2d data-reuse architecture \" in ISSCC'19 pp. 138--140."},{"key":"e_1_3_2_2_11_1","first-page":"315","volume-title":"Resirca: A resilient energy harvesting reram crossbar-based accelerator for intelligent embedded processors,\" in HPCA'20","author":"Qiu K.","unstructured":"K. Qiu , N. Jao , M. Zhao , C. S. Mishra , G. Gudukbay , S. Jose , J. Sampson , M. T. Kandemir , and V. Narayanan , \" Resirca: A resilient energy harvesting reram crossbar-based accelerator for intelligent embedded processors,\" in HPCA'20 , pp. 315 -- 327 . K. Qiu, N. Jao, M. Zhao, C. S. Mishra, G. Gudukbay, S. Jose, J. Sampson, M. T. Kandemir, and V. Narayanan, \"Resirca: A resilient energy harvesting reram crossbar-based accelerator for intelligent embedded processors,\" in HPCA'20, pp. 315--327."},{"key":"e_1_3_2_2_12_1","first-page":"149","volume-title":"A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops,\" in ESSCIRC'12","author":"Wang Y.","unstructured":"Y. Wang , Y. Liu , S. Li , D. Zhang , B. Zhao , M.-F. Chiang , Y. Yan , B. Sai , and H. Yang , \" A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops,\" in ESSCIRC'12 , pp. 149 -- 152 . Y. Wang, Y. Liu, S. Li, D. Zhang, B. Zhao, M.-F. Chiang, Y. Yan, B. Sai, and H. Yang, \"A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops,\" in ESSCIRC'12, pp. 149--152."},{"volume-title":"Advancing nonvolatile computing with nonvolatile NCFET latches and flip-flops,\" TCAS-I'17","author":"Li X.","key":"e_1_3_2_2_13_1","unstructured":"X. Li , S. George , K. Ma , W. Tsai , A. Aziz , J. Sampson , S. K. Gupta , M. Chang , Y. Liu , S. Datta , and V. Narayanan , \" Advancing nonvolatile computing with nonvolatile NCFET latches and flip-flops,\" TCAS-I'17 , vol. 64 , no. 11, pp. 2907--2919. X. Li, S. George, K. Ma, W. Tsai, A. Aziz, J. Sampson, S. K. Gupta, M. Chang, Y. Liu, S. Datta, and V. Narayanan, \"Advancing nonvolatile computing with nonvolatile NCFET latches and flip-flops,\" TCAS-I'17, vol. 64, no. 11, pp. 2907--2919."},{"key":"e_1_3_2_2_14_1","first-page":"1","volume-title":"Dual mode ferroelectric transistor based non-volatile flip-flops for intermittently-powered systems,\" in ISLPED'18","author":"Thirumala S. K.","unstructured":"S. K. Thirumala , A. Raha , H. Jayakumar , K. Ma , V. Narayanan , V. Raghunathan , and S. K. Gupta , \" Dual mode ferroelectric transistor based non-volatile flip-flops for intermittently-powered systems,\" in ISLPED'18 , pp. 1 -- 6 . S. K. Thirumala, A. Raha, H. Jayakumar, K. Ma, V. Narayanan, V. Raghunathan, and S. K. Gupta, \"Dual mode ferroelectric transistor based non-volatile flip-flops for intermittently-powered systems,\" in ISLPED'18, pp. 1--6."},{"key":"e_1_3_2_2_15_1","first-page":"84","volume-title":"4.7 a 65nm reram-enabled nonvolatile processor with 6\u00d7 reduction in restore time and 4\u00d7 higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic,\" in ISSCC'16","author":"Liu Y.","unstructured":"Y. Liu , Z. Wang , A. Lee , F. Su , C. Lo , Z. Yuan , C. Lin , Q. Wei , Y. Wang , Y. King , C. Lin , P. Khalili , K. Wang , M. Chang , and H. Yang , \" 4.7 a 65nm reram-enabled nonvolatile processor with 6\u00d7 reduction in restore time and 4\u00d7 higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic,\" in ISSCC'16 , pp. 84 -- 86 . Y. Liu, Z. Wang, A. Lee, F. Su, C. Lo, Z. Yuan, C. Lin, Q. Wei, Y. Wang, Y. King, C. Lin, P. Khalili, K. Wang, M. Chang, and H. Yang, \"4.7 a 65nm reram-enabled nonvolatile processor with 6\u00d7 reduction in restore time and 4\u00d7 higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic,\" in ISSCC'16, pp. 84--86."},{"volume-title":"A reram-based nonvolatile flip-flop with self-write-termination scheme for frequent-off fast-wake-up nonvolatile processors,\" JSSC'17","author":"Lee A.","key":"e_1_3_2_2_16_1","unstructured":"A. Lee , C. Lo , C. Lin , W. Chen , K. Hsu , Z. Wang , F. Su , Z. Yuan , Q. Wei , Y. King , C. Lin , H. Lee , P. Khalili Amiri , K. Wang , Y. Wang , H. Yang , Y. Liu , and M. Chang , \" A reram-based nonvolatile flip-flop with self-write-termination scheme for frequent-off fast-wake-up nonvolatile processors,\" JSSC'17 , vol. 52 , no. 8, pp. 2194--2207. A. Lee, C. Lo, C. Lin, W. Chen, K. Hsu, Z. Wang, F. Su, Z. Yuan, Q. Wei, Y. King, C. Lin, H. Lee, P. Khalili Amiri, K. Wang, Y. Wang, H. Yang, Y. Liu, and M. Chang, \"A reram-based nonvolatile flip-flop with self-write-termination scheme for frequent-off fast-wake-up nonvolatile processors,\" JSSC'17, vol. 52, no. 8, pp. 2194--2207."},{"volume-title":"A 3.4-pj feram-enabled d flip-flop in 0.13-\u03bc hboxm$ cmos for nonvolatile processing in digital systems,\" JSSC'14","author":"Qazi M.","key":"e_1_3_2_2_17_1","unstructured":"M. Qazi , A. Amerasekera , and A. P. Chandrakasan , \" A 3.4-pj feram-enabled d flip-flop in 0.13-\u03bc hboxm$ cmos for nonvolatile processing in digital systems,\" JSSC'14 , vol. 49 , no. 1, pp. 202--211. M. Qazi, A. Amerasekera, and A. P. Chandrakasan, \"A 3.4-pj feram-enabled d flip-flop in 0.13-\u03bc hboxm$ cmos for nonvolatile processing in digital systems,\" JSSC'14, vol. 49, no. 1, pp. 202--211."},{"key":"e_1_3_2_2_18_1","unstructured":"\"Texas instruments. [online]. available: www.ti.com\/product\/cc1101 \"  \"Texas instruments. [online]. available: www.ti.com\/product\/cc1101 \""},{"key":"e_1_3_2_2_19_1","doi-asserted-by":"crossref","unstructured":"F. Su W. Chen L. Xia C. Lo T. Tang Z. Wang K. Hsu M. Cheng J. Li Y. Xie Y. Wang M. Chang H. Yang and Y. Liu \"A 462gops\/j rram-based nonvolatile intelligent processor for energy harvesting ioe system featuring nonvolatile logics and processing-in-memory \" in 2017 Symposium on VLSI Circuits pp. C260--C261.  F. Su W. Chen L. Xia C. Lo T. Tang Z. Wang K. Hsu M. Cheng J. Li Y. Xie Y. Wang M. Chang H. Yang and Y. Liu \"A 462gops\/j rram-based nonvolatile intelligent processor for energy harvesting ioe system featuring nonvolatile logics and processing-in-memory \" in 2017 Symposium on VLSI Circuits pp. C260--C261.","DOI":"10.23919\/VLSIC.2017.8008585"},{"key":"e_1_3_2_2_20_1","doi-asserted-by":"crossref","unstructured":"Y. Zha E. Nowak and J. Li \"Liquid silicon: A nonvolatile fully programmable processing-in-memory processor with monolithically integrated reram for big data\/machine learning applications \" in 2019 Symposium on VLSI Circuits pp. C206--C207.  Y. Zha E. Nowak and J. Li \"Liquid silicon: A nonvolatile fully programmable processing-in-memory processor with monolithically integrated reram for big data\/machine learning applications \" in 2019 Symposium on VLSI Circuits pp. C206--C207.","DOI":"10.23919\/VLSIC.2019.8778064"},{"key":"e_1_3_2_2_21_1","first-page":"1491","volume-title":"PaCC: A parallel compare and compress codec for area reduction in nonvolatile processors,\" TVLSI'13","author":"Wang Y.","unstructured":"Y. Wang , Y. Liu , S. Li , X. Sheng , D. Zhang , M.-F. Chiang , B. Sai , X. Hu , and H. Yang , \" PaCC: A parallel compare and compress codec for area reduction in nonvolatile processors,\" TVLSI'13 , vol. PP, no. 99 , pp. 1491 -- 1505 . Y. Wang, Y. Liu, S. Li, X. Sheng, D. Zhang, M.-F. Chiang, B. Sai, X. Hu, and H. Yang, \"PaCC: A parallel compare and compress codec for area reduction in nonvolatile processors,\" TVLSI'13, vol. PP, no. 99, pp. 1491--1505."},{"key":"e_1_3_2_2_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2983990.2983995"},{"volume-title":"A simpler, safer programming and execution model for intermittent systems,\" PLDI'15","author":"Lucia B.","key":"e_1_3_2_2_23_1","unstructured":"B. Lucia and B. Ransford , \" A simpler, safer programming and execution model for intermittent systems,\" PLDI'15 , vol. 50 , no. 6, pp. 575--585. B. Lucia and B. Ransford, \"A simpler, safer programming and execution model for intermittent systems,\" PLDI'15, vol. 50, no. 6, pp. 575--585."},{"key":"e_1_3_2_2_24_1","first-page":"1","volume-title":"Checkpoint aware hybrid cache architecture for nv processor in energy harvesting powered systems,\" in CODES+ISSS'16","author":"Xie M.","unstructured":"M. Xie , M. Zhao , C. Pan , H. Li , Y. Liu , Y. Zhang , C. J. Xue , and J. Hu , \" Checkpoint aware hybrid cache architecture for nv processor in energy harvesting powered systems,\" in CODES+ISSS'16 , pp. 1 -- 10 , Oct. M. Xie, M. Zhao, C. Pan, H. Li, Y. Liu, Y. Zhang, C. J. Xue, and J. Hu, \"Checkpoint aware hybrid cache architecture for nv processor in energy harvesting powered systems,\" in CODES+ISSS'16, pp. 1--10, Oct."},{"volume-title":"Quickrecall: A hw\/sw approach for computing across power cycles in transiently powered computers,\" JETC'15","author":"Jayakumar H.","key":"e_1_3_2_2_25_1","unstructured":"H. Jayakumar , A. Raha , W. S. Lee , and V. Raghunathan , \" Quickrecall: A hw\/sw approach for computing across power cycles in transiently powered computers,\" JETC'15 , vol. 12 , no. 1. H. Jayakumar, A. Raha, W. S. Lee, and V. Raghunathan, \"Quickrecall: A hw\/sw approach for computing across power cycles in transiently powered computers,\" JETC'15, vol. 12, no. 1."},{"key":"e_1_3_2_2_26_1","first-page":"526","volume-title":"Architecture exploration for ambient energy harvesting nonvolatile processors,\" in HPCA'15","author":"Ma K.","unstructured":"K. Ma , Y. Zheng , S. Li , K. Swaminathan , X. Li , Y. Liu , J. Sampson , Y. Xie , and V. Narayanan , \" Architecture exploration for ambient energy harvesting nonvolatile processors,\" in HPCA'15 , pp. 526 -- 537 . K. Ma, Y. Zheng, S. Li, K. Swaminathan, X. Li, Y. Liu, J. Sampson, Y. Xie, and V. Narayanan, \"Architecture exploration for ambient energy harvesting nonvolatile processors,\" in HPCA'15, pp. 526--537."},{"volume-title":"Embedded memory and arm cortex-m0 core using 60-nm c-axis aligned crystalline indium--gallium--zinc oxide fet integrated with 65-nm si cmos,\" JSSC'17","author":"Onuki T.","key":"e_1_3_2_2_27_1","unstructured":"T. Onuki , W. Uesugi , A. Isobe , Y. Ando , S. Okamoto , K. Kato , T. R. Yew , J. Y. Wu , C. C. Shuai , S. H. Wu , J. Myers , K. Doppler , M. Fujita , and S. Yamazaki , \" Embedded memory and arm cortex-m0 core using 60-nm c-axis aligned crystalline indium--gallium--zinc oxide fet integrated with 65-nm si cmos,\" JSSC'17 , vol. 52 , no. 4, pp. 925--932. T. Onuki, W. Uesugi, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T. R. Yew, J. Y. Wu, C. C. Shuai, S. H. Wu, J. Myers, K. Doppler, M. Fujita, and S. Yamazaki, \"Embedded memory and arm cortex-m0 core using 60-nm c-axis aligned crystalline indium--gallium--zinc oxide fet integrated with 65-nm si cmos,\" JSSC'17, vol. 52, no. 4, pp. 925--932."},{"key":"e_1_3_2_2_28_1","first-page":"395","volume-title":"CirCNN: Accelerating and compressing deep neural networks using block-circulant weight matrices,\" in MICRO'17","author":"Ding C.","unstructured":"C. Ding , S. Liao , Y. Wang , Z. Li , N. Liu , Y. Zhuo , C. Wang , X. Qian , Y. Bai , G. Yuan , X. Ma , Y. Zhang , J. Tang , Q. Qiu , X. Lin , and B. Yuan , \" CirCNN: Accelerating and compressing deep neural networks using block-circulant weight matrices,\" in MICRO'17 , p. 395 -- 408 . C. Ding, S. Liao, Y. Wang, Z. Li, N. Liu, Y. Zhuo, C. Wang, X. Qian, Y. Bai, G. Yuan, X. Ma, Y. Zhang, J. Tang, Q. Qiu, X. Lin, and B. Yuan, \"CirCNN: Accelerating and compressing deep neural networks using block-circulant weight matrices,\" in MICRO'17, p. 395--408."},{"key":"e_1_3_2_2_29_1","first-page":"1","volume-title":"Non-volatile registers aware instruction selection for embedded systems,\" in RTCSA'14","author":"Xie M.","unstructured":"M. Xie , C. Pan , J. Hu , C. J. Xue , and Q. Zhuge , \" Non-volatile registers aware instruction selection for embedded systems,\" in RTCSA'14 , pp. 1 -- 9 . M. Xie, C. Pan, J. Hu, C. J. Xue, and Q. Zhuge, \"Non-volatile registers aware instruction selection for embedded systems,\" in RTCSA'14, pp. 1--9."},{"key":"e_1_3_2_2_30_1","first-page":"1","volume-title":"Compiler directed automatic stack trimming for efficient non-volatile processors,\" in DAC'15","author":"Li Q.","unstructured":"Q. Li , M. Zhao , J. Hu , Y. Liu , Y. He , and C. J. Xue , \" Compiler directed automatic stack trimming for efficient non-volatile processors,\" in DAC'15 , pp. 1 -- 6 . Q. Li, M. Zhao, J. Hu, Y. Liu, Y. He, and C. J. Xue, \"Compiler directed automatic stack trimming for efficient non-volatile processors,\" in DAC'15, pp. 1--6."},{"volume-title":"EMC: Energy-aware morphable cache design for non-volatile processors,\" TC'19","author":"Song W.","key":"e_1_3_2_2_31_1","unstructured":"W. Song , Y. Zhou , M. Zhao , L. Ju , C. J. Xue , and Z. Jia , \" EMC: Energy-aware morphable cache design for non-volatile processors,\" TC'19 , vol. 68 , no. 4, pp. 498--509. W. Song, Y. Zhou, M. Zhao, L. Ju, C. J. Xue, and Z. Jia, \"EMC: Energy-aware morphable cache design for non-volatile processors,\" TC'19, vol. 68, no. 4, pp. 498--509."},{"key":"e_1_3_2_2_32_1","first-page":"129","volume-title":"Adaptive dynamic checkpointing for safe efficient intermittent computing,\" in OSDI'18","author":"Maeng K.","unstructured":"K. Maeng and B. Lucia , \" Adaptive dynamic checkpointing for safe efficient intermittent computing,\" in OSDI'18 , pp. 129 -- 144 . K. Maeng and B. Lucia, \"Adaptive dynamic checkpointing for safe efficient intermittent computing,\" in OSDI'18, pp. 129--144."},{"key":"e_1_3_2_2_33_1","first-page":"5","volume-title":"Getting things done on computational rfids with energy-aware checkpointing and voltage-aware scheduling,\" in Proceedings of the 2008 Conference on Power Aware Computing and Systems","author":"Ransford B.","unstructured":"B. Ransford , S. S. Clark , M. Salajegheh , and K. Fu , \" Getting things done on computational rfids with energy-aware checkpointing and voltage-aware scheduling,\" in Proceedings of the 2008 Conference on Power Aware Computing and Systems , pp. 5 -- 5 . B. Ransford, S. S. Clark, M. Salajegheh, and K. Fu, \"Getting things done on computational rfids with energy-aware checkpointing and voltage-aware scheduling,\" in Proceedings of the 2008 Conference on Power Aware Computing and Systems, pp. 5--5."},{"volume-title":"Stack-size sensitive on-chip memory backup for self-powered nonvolatile processors,\" TCAD'17","author":"Zhao M.","key":"e_1_3_2_2_34_1","unstructured":"M. Zhao , C. Fu , Z. Li , Q. Li , M. Xie , Y. Liu , J. Hu , Z. Jia , and C. J. Xue , \" Stack-size sensitive on-chip memory backup for self-powered nonvolatile processors,\" TCAD'17 , vol. 36 , no. 11, pp. 1804--1816. M. Zhao, C. Fu, Z. Li, Q. Li, M. Xie, Y. Liu, J. Hu, Z. Jia, and C. J. Xue, \"Stack-size sensitive on-chip memory backup for self-powered nonvolatile processors,\" TCAD'17, vol. 36, no. 11, pp. 1804--1816."},{"key":"e_1_3_2_2_35_1","first-page":"1","volume-title":"Maximizing forward progress with cache-aware backup for self-powered non-volatile processors,\" in DAC'17","author":"Li J.","unstructured":"J. Li , M. Zhao , L. Ju , C. J. Xue , and Z. Jia , \" Maximizing forward progress with cache-aware backup for self-powered non-volatile processors,\" in DAC'17 , pp. 1 -- 6 . J. Li, M. Zhao, L. Ju, C. J. Xue, and Z. Jia, \"Maximizing forward progress with cache-aware backup for self-powered non-volatile processors,\" in DAC'17, pp. 1--6."},{"key":"e_1_3_2_2_36_1","first-page":"1247","volume-title":"Q-learning based backup for energy harvesting powered embedded systems,\" in DATE'20","author":"Fan W.","unstructured":"W. Fan , Y. Zhang , W. Song , M. Zhao , Z. Shen , and Z. Jia , \" Q-learning based backup for energy harvesting powered embedded systems,\" in DATE'20 , pp. 1247 -- 1252 . W. Fan, Y. Zhang, W. Song, M. Zhao, Z. Shen, and Z. Jia, \"Q-learning based backup for energy harvesting powered embedded systems,\" in DATE'20, pp. 1247--1252."},{"key":"e_1_3_2_2_37_1","first-page":"1","volume-title":"Nonvolatile memory is a broken time machine,\" in Proceedings of the workshop on MMSPC'14","author":"Ransford B.","unstructured":"B. Ransford and B. Lucia , \" Nonvolatile memory is a broken time machine,\" in Proceedings of the workshop on MMSPC'14 , pp. 1 -- 3 . B. Ransford and B. Lucia, \"Nonvolatile memory is a broken time machine,\" in Proceedings of the workshop on MMSPC'14, pp. 1--3."},{"key":"e_1_3_2_2_38_1","first-page":"1","volume-title":"Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor,\" in DAC'15","author":"Xie M.","unstructured":"M. Xie , M. Zhao , C. Pan , J. Hu , Y. Liu , and C. J. Xue , \" Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor,\" in DAC'15 , pp. 184: 1 -- 184 :6. M. Xie, M. Zhao, C. Pan, J. Hu, Y. Liu, and C. J. Xue, \"Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor,\" in DAC'15, pp. 184:1--184:6."},{"key":"e_1_3_2_2_39_1","volume-title":"ACM Program. Lang. (OOPSLA)","volume":"3","author":"Surbatovich M.","year":"2019","unstructured":"M. Surbatovich , L. Jia , and B. Lucia , \" I\/O dependent idempotence bugs in intermittent systems,\" Proc . ACM Program. Lang. (OOPSLA) , vol. 3 , 2019 . M. Surbatovich, L. Jia, and B. Lucia, \"I\/O dependent idempotence bugs in intermittent systems,\" Proc. ACM Program. Lang. (OOPSLA), vol. 3, 2019."},{"key":"e_1_3_2_2_40_1","first-page":"247","volume-title":"RTSS'16","author":"Chen W.-M.","unstructured":"W.-M. Chen , T.-S. Cheng , P.-C. Hsiu , and T.-W. Kuo , \" Value-Based Task Scheduling for Nonvolatile Processor-Based Embedded Devices,\" in RTSS'16 , pp. 247 -- 256 . W.-M. Chen, T.-S. Cheng, P.-C. Hsiu, and T.-W. Kuo, \"Value-Based Task Scheduling for Nonvolatile Processor-Based Embedded Devices,\" in RTSS'16, pp. 247--256."},{"key":"e_1_3_2_2_41_1","first-page":"1","volume-title":"DAC'19","author":"Chen W.-M.","unstructured":"W.-M. Chen , P.-C. Hsiu , and T.-W. Kuo , \" Enabling Failure-resilient Intermittently-powered Systems Without Runtime Checkpointing ,\" in DAC'19 , pp. 104: 1 -- 6 . W.-M. Chen, P.-C. Hsiu, and T.-W. Kuo, \"Enabling Failure-resilient Intermittently-powered Systems Without Runtime Checkpointing,\" in DAC'19, pp. 104:1--6."},{"key":"e_1_3_2_2_42_1","first-page":"1","volume-title":"ICCAD'19","author":"Chen W.-M.","unstructured":"W.-M. Chen , Y.-T. Chen , P.-C. Hsiu , and T.-W. Kuo , \" Multiversion Concurrency Control on Intermittent Systems ,\" in ICCAD'19 , pp. 1 -- 8 . W.-M. Chen, Y.-T. Chen, P.-C. Hsiu, and T.-W. Kuo, \"Multiversion Concurrency Control on Intermittent Systems,\" in ICCAD'19, pp. 1--8."},{"key":"e_1_3_2_2_43_1","unstructured":"W.-M. Chen T.-W. Kuo and P.-C. Hsiu \"Enabling failure-resilient intermittent systems without runtime checkpointing \" TCAD'20 Early Access.  W.-M. Chen T.-W. Kuo and P.-C. Hsiu \"Enabling failure-resilient intermittent systems without runtime checkpointing \" TCAD'20 Early Access."},{"key":"e_1_3_2_2_44_1","unstructured":"https:\/\/github.com\/EMCLab-Sinica\/Intermittent-OS\/.  https:\/\/github.com\/EMCLab-Sinica\/Intermittent-OS\/."},{"key":"e_1_3_2_2_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/3133920"},{"key":"e_1_3_2_2_46_1","first-page":"1005","volume-title":"Adaptive low-overhead scheduling for periodic and reactive intermittent execution,\" in PLDI'20","author":"Maeng K.","unstructured":"K. Maeng and B. Lucia , \" Adaptive low-overhead scheduling for periodic and reactive intermittent execution,\" in PLDI'20 , p. 1005 -- 1021 . K. Maeng and B. Lucia, \"Adaptive low-overhead scheduling for periodic and reactive intermittent execution,\" in PLDI'20, p. 1005--1021."},{"key":"e_1_3_2_2_47_1","first-page":"767","volume-title":"A reconfigurable energy storage architecture for energy-harvesting devices,\" in ASPLOS'18","author":"Colin A.","unstructured":"A. Colin , E. Ruppel , and B. Lucia , \" A reconfigurable energy storage architecture for energy-harvesting devices,\" in ASPLOS'18 , pp. 767 -- 781 . A. Colin, E. Ruppel, and B. Lucia, \"A reconfigurable energy storage architecture for energy-harvesting devices,\" in ASPLOS'18, pp. 767--781."},{"key":"e_1_3_2_2_48_1","first-page":"670","volume-title":"Dynamic machine learning based matching of nonvolatile processor microarchitecture to harvested energy profile,\" in ICCAD'15","author":"Ma K.","unstructured":"K. Ma , X. Li , Y. Liu , J. Sampson , Y. Xie , and V. Narayanan , \" Dynamic machine learning based matching of nonvolatile processor microarchitecture to harvested energy profile,\" in ICCAD'15 , pp. 670 -- 675 . K. Ma, X. Li, Y. Liu, J. Sampson, Y. Xie, and V. Narayanan, \"Dynamic machine learning based matching of nonvolatile processor microarchitecture to harvested energy profile,\" in ICCAD'15, pp. 670--675."},{"key":"e_1_3_2_2_49_1","first-page":"678","volume-title":"Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors,\" in ASP-DAC'17","author":"Ma K.","unstructured":"K. Ma , X. Li , S. R. Srinivasa , Y. Liu , J. Sampson , Y. Xie , and V. Narayanan , \" Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors,\" in ASP-DAC'17 , pp. 678 -- 683 . K. Ma, X. Li, S. R. Srinivasa, Y. Liu, J. Sampson, Y. Xie, and V. Narayanan, \"Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors,\" in ASP-DAC'17, pp. 678--683."},{"key":"e_1_3_2_2_50_1","first-page":"204","volume-title":"Incidental computing on iot nonvolatile processors,\" in MICRO'17","author":"Ma K.","unstructured":"K. Ma , X. Li , J. Li , Y. Liu , Y. Xie , J. Sampson , M. T. Kandemir , and V. Narayanan , \" Incidental computing on iot nonvolatile processors,\" in MICRO'17 , pp. 204 -- 218 . K. Ma, X. Li, J. Li, Y. Liu, Y. Xie, J. Sampson, M. T. Kandemir, and V. Narayanan, \"Incidental computing on iot nonvolatile processors,\" in MICRO'17, pp. 204--218."},{"volume-title":"Iaa: Incidental approximate architectures for extremely energy-constrained energy harvesting scenarios using iot nonvolatile processors,\" IEEE Micro'18","author":"Ma K.","key":"e_1_3_2_2_51_1","unstructured":"K. Ma , J. Li , X. Li , Y. Liu , Y. Xie , M. Kandemir , J. Sampson , and V. Narayanan , \" Iaa: Incidental approximate architectures for extremely energy-constrained energy harvesting scenarios using iot nonvolatile processors,\" IEEE Micro'18 , vol. 38 , no. 4, pp. 11--19. K. Ma, J. Li, X. Li, Y. Liu, Y. Xie, M. Kandemir, J. Sampson, and V. Narayanan, \"Iaa: Incidental approximate architectures for extremely energy-constrained energy harvesting scenarios using iot nonvolatile processors,\" IEEE Micro'18, vol. 38, no. 4, pp. 11--19."},{"key":"e_1_3_2_2_52_1","first-page":"782","volume-title":"NEOFog: Nonvolatility-exploiting optimizations for fog computing,\" in ASPLOS'18","author":"Ma K.","unstructured":"K. Ma , X. Li , M. T. Kandemir , J. Sampson , V. Narayanan , J. Li , T. Wu , Z. Wang , Y. Liu , and Y. Xie , \" NEOFog: Nonvolatility-exploiting optimizations for fog computing,\" in ASPLOS'18 , pp. 782 -- 796 . K. Ma, X. Li, M. T. Kandemir, J. Sampson, V. Narayanan, J. Li, T. Wu, Z. Wang, Y. Liu, and Y. Xie, \"NEOFog: Nonvolatility-exploiting optimizations for fog computing,\" in ASPLOS'18, pp. 782--796."},{"volume-title":"Dynamic task-based intermittent execution for energy-harvesting devices,\" TSN'20","author":"Majid A. Y.","key":"e_1_3_2_2_53_1","unstructured":"A. Y. Majid , C. D. Donne , K. Maeng , A. Colin , K. S. Yildirim , B. Lucia , and P. Pawe\u0142czak , \" Dynamic task-based intermittent execution for energy-harvesting devices,\" TSN'20 , vol. 16 , no. 1. A. Y. Majid, C. D. Donne, K. Maeng, A. Colin, K. S. Yildirim, B. Lucia, and P. Pawe\u0142czak, \"Dynamic task-based intermittent execution for energy-harvesting devices,\" TSN'20, vol. 16, no. 1."},{"key":"e_1_3_2_2_54_1","unstructured":"B. L. Graham Gobieski Nathan Beckmann \"Intermittent deep neural network inference \" in SysML Conference pp. 1--3 2018.  B. L. Graham Gobieski Nathan Beckmann \"Intermittent deep neural network inference \" in SysML Conference pp. 1--3 2018."},{"key":"e_1_3_2_2_55_1","first-page":"199","volume-title":"Intelligence beyond the edge: Inference on intermittent embedded systems,\" in ASPLOS '19","author":"Gobieski G.","year":"2019","unstructured":"G. Gobieski , B. Lucia , and N. Beckmann , \" Intelligence beyond the edge: Inference on intermittent embedded systems,\" in ASPLOS '19 , p. 199 -- 213 , 2019 . G. Gobieski, B. Lucia, and N. Beckmann, \"Intelligence beyond the edge: Inference on intermittent embedded systems,\" in ASPLOS '19, p. 199--213, 2019."}],"event":{"name":"GLSVLSI '20: Great Lakes Symposium on VLSI 2020","acronym":"GLSVLSI '20","location":"Virtual Event China"},"container-title":["Proceedings of the 2020 on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3407596","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3386263.3407596","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:38:25Z","timestamp":1750199905000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3407596"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,7]]},"references-count":55,"alternative-id":["10.1145\/3386263.3407596","10.1145\/3386263"],"URL":"https:\/\/doi.org\/10.1145\/3386263.3407596","relation":{},"subject":[],"published":{"date-parts":[[2020,9,7]]},"assertion":[{"value":"2020-09-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}