{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,23]],"date-time":"2026-01-23T20:01:06Z","timestamp":1769198466133,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,9,7]],"date-time":"2020-09-07T00:00:00Z","timestamp":1599436800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Natural Science Foundation of China","award":["61832007, 61622403, 61621091, U19B2019"],"award-info":[{"award-number":["61832007, 61622403, 61621091, U19B2019"]}]},{"name":"Beijing Academy of Artificial Intelligence under Grant","award":["BAAI2019QN0402"],"award-info":[{"award-number":["BAAI2019QN0402"]}]},{"name":"National Key Research and Development Program of China","award":["2017YFA0207600"],"award-info":[{"award-number":["2017YFA0207600"]}]},{"name":"Beijing National Research Center for Information Science and Technology","award":["BNRist"],"award-info":[{"award-number":["BNRist"]}]},{"name":"Beijing Innovation Center for Future Chips"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,9,7]]},"DOI":"10.1145\/3386263.3407647","type":"proceedings-article","created":{"date-parts":[[2020,9,4]],"date-time":"2020-09-04T21:34:23Z","timestamp":1599255263000},"page":"83-88","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":69,"title":["MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems"],"prefix":"10.1145","author":[{"given":"Zhenhua","family":"Zhu","sequence":"first","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Hanbo","family":"Sun","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Kaizhong","family":"Qiu","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Lixue","family":"Xia","sequence":"additional","affiliation":[{"name":"Alibaba Group, Beijing, China"}]},{"given":"Gokul","family":"Krishnan","sequence":"additional","affiliation":[{"name":"Arizona State University, Phoenix, AZ, USA"}]},{"given":"Guohao","family":"Dai","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Dimin","family":"Niu","sequence":"additional","affiliation":[{"name":"Alibaba Group, Sunnyvale, CA, USA"}]},{"given":"Xiaoming","family":"Chen","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}]},{"given":"X. Sharon","family":"Hu","sequence":"additional","affiliation":[{"name":"University of Notre Dame, Notre Dame, IN, USA"}]},{"given":"Yu","family":"Cao","sequence":"additional","affiliation":[{"name":"Arizona State University, Phoenix, AZ, USA"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[{"name":"University of California, Santa Barbara, Santa Barbara, CA, USA"}]},{"given":"Yu","family":"Wang","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Huazhong","family":"Yang","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2020,9,7]]},"reference":[{"key":"e_1_3_2_2_1_1","first-page":"97","article-title":"A &gt;3GHz ERBW 1.1GS\/s 8b Two-Sten SAR ADC with Recursive-Weight DAC","volume":"2018","author":"Chen H.","year":"2018","unstructured":"H. Chen 2018 . A &gt;3GHz ERBW 1.1GS\/s 8b Two-Sten SAR ADC with Recursive-Weight DAC . In VLSI-Circuits , 2018. 97 -- 98 . H. Chen et al. 2018. A &gt;3GHz ERBW 1.1GS\/s 8b Two-Sten SAR ADC with Recursive-Weight DAC. In VLSI-Circuits, 2018. 97--98.","journal-title":"VLSI-Circuits"},{"key":"e_1_3_2_2_2_1","volume-title":"ISCA","year":"2016","unstructured":"P.Chietal.2016.PRIME:ANovelProcessing-in-memoryArchitectureforNeural Network Computation in ReRAM-based Main Memory. In ISCA , 2016 . P.Chietal.2016.PRIME:ANovelProcessing-in-memoryArchitectureforNeural Network Computation in ReRAM-based Main Memory. In ISCA, 2016."},{"key":"e_1_3_2_2_3_1","first-page":"460","article-title":"27.3 Area-efficient 1GS\/s 6b SAR ADC with charge-injection-cell-based DAC","volume":"2016","author":"Choo K. D.","year":"2016","unstructured":"K. D. Choo , J. Bell , and M. P. Flynn . 2016 . 27.3 Area-efficient 1GS\/s 6b SAR ADC with charge-injection-cell-based DAC . In ISSCC , 2016. 460 -- 461 . K. D. Choo, J. Bell, and M. P. Flynn. 2016. 27.3 Area-efficient 1GS\/s 6b SAR ADC with charge-injection-cell-based DAC. In ISSCC, 2016. 460--461.","journal-title":"ISSCC"},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"crossref","unstructured":"X. Dong etal 2012. NVSim: A Circuit-Level Performance Energy and Area Model for Emerging Nonvolatile Memory. IEEE TCAD (2012).  X. Dong et al. 2012. NVSim: A Circuit-Level Performance Energy and Area Model for Emerging Nonvolatile Memory. IEEE TCAD (2012).","DOI":"10.1007\/978-1-4419-9551-3_2"},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"e_1_3_2_2_6_1","first-page":"1","article-title":"Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping","volume":"2019","author":"He Z.","year":"2019","unstructured":"Z. He 2019 . Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping . In DAC , 2019. 1 -- 6 . Z. He et al. 2019. Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping. In DAC, 2019. 1--6.","journal-title":"DAC"},{"key":"e_1_3_2_2_7_1","unstructured":"Kaggle etal 2014. CIFAR-10 - Object Recognition in Images. website. (2014). https:\/\/www.kaggle.com\/c\/cifar-10.  Kaggle et al. 2014. CIFAR-10 - Object Recognition in Images. website. (2014). https:\/\/www.kaggle.com\/c\/cifar-10."},{"key":"e_1_3_2_2_8_1","unstructured":"S. Karen etal 2014. Very Deep Convolutional Networks for Large-Scale Image Recognition. Computer Science (2014).  S. Karen et al. 2014. Very Deep Convolutional Networks for Large-Scale Image Recognition. Computer Science (2014)."},{"key":"e_1_3_2_2_9_1","unstructured":"G. Krishnan etal 2020. Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs. IEEE Design and Test (2020) 1--1.  G. Krishnan et al. 2020. Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs. IEEE Design and Test (2020) 1--1."},{"key":"e_1_3_2_2_10_1","first-page":"474","article-title":"28.5 A 10b 1.5GS\/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET","volume":"2017","author":"Kull L.","year":"2017","unstructured":"L. Kull 2017 . 28.5 A 10b 1.5GS\/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET . In ISSCC , 2017. 474 -- 475 . L. Kull et al. 2017. 28.5 A 10b 1.5GS\/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. In ISSCC, 2017. 474--475.","journal-title":"ISSCC"},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"e_1_3_2_2_12_1","first-page":"1","article-title":"DL-RSIM: A Simulation Framework to Enable Reliable ReRAM-based Accelerators for Deep Learning","volume":"2018","year":"2018","unstructured":"M.Lin 2018 . DL-RSIM: A Simulation Framework to Enable Reliable ReRAM-based Accelerators for Deep Learning . In ICCAD , 2018. 1 -- 8 . M.Lin et al. 2018. DL-RSIM: A Simulation Framework to Enable Reliable ReRAM-based Accelerators for Deep Learning. In ICCAD, 2018. 1--8.","journal-title":"ICCAD"},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3358176"},{"key":"e_1_3_2_2_14_1","first-page":"1","article-title":"A700","volume":"2017","author":"Nasri B.","year":"2017","unstructured":"B. Nasri 2017 . A700 \"\"W 1GS\/s 4-bit folding-flash ADC in 65nm CMOS for wide band wireless communications. In ISCAS , 2017. 1 -- 4 . B. Nasri et al.2017. A700 \"\"W 1GS\/s 4-bit folding-flash ADC in 65nm CMOS for wide band wireless communications. In ISCAS, 2017. 1--4.","journal-title":"In ISCAS"},{"key":"e_1_3_2_2_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993491"},{"key":"e_1_3_2_2_16_1","volume-title":"ISCA","author":"Shafiee A.","year":"2016","unstructured":"A. Shafiee 2016 . ISAAC: A Convolutional Neural Network Accelerator with In-situ Analog Arithmetic in Crossbars . In ISCA , 2016. A. Shafiee et al. 2016. ISAAC: A Convolutional Neural Network Accelerator with In-situ Analog Arithmetic in Crossbars. In ISCA, 2016."},{"key":"e_1_3_2_2_17_1","first-page":"1","article-title":"An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators","volume":"2020","author":"Sun H.","year":"2020","unstructured":"H. Sun 2020 . An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators . In ASPDAC , 2020. 1 -- 6 . H. Sun et al. 2020. An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators. In ASPDAC, 2020. 1--6.","journal-title":"ASPDAC"},{"key":"e_1_3_2_2_18_1","volume-title":"JSSC, 1996","author":"Wilton S. J. E.","year":"1996","unstructured":"S. J. E. Wilton and N. P. Jouppi . 1996. CACTI: an enhanced cache access and cycle time model . JSSC, 1996 31, 5 ( 1996 ), 677--688. S. J. E. Wilton and N. P. Jouppi. 1996. CACTI: an enhanced cache access and cycle time model. JSSC, 1996 31, 5 (1996), 677--688."},{"key":"e_1_3_2_2_19_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.5037896"},{"key":"e_1_3_2_2_20_1","first-page":"2018","volume-title":"TCAD","author":"Xia L.","year":"2018","unstructured":"L. Xia 2018 . MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System . TCAD , 2018 (2018). L. Xia et al. 2018. MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. TCAD, 2018 (2018)."},{"key":"e_1_3_2_2_21_1","first-page":"1","article-title":"Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis","volume":"2019","author":"Zhang W.","year":"2019","unstructured":"W. Zhang 2019 . Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis . In DAC , 2019. 1 -- 6 . W. Zhang et al. 2019. Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis. In DAC, 2019. 1--6.","journal-title":"DAC"},{"key":"e_1_3_2_2_22_1","first-page":"1","article-title":"A Configurable Multi-Precision CNN Computing Framework Based on Single Bit RRAM","volume":"2019","author":"Zhu Z.","year":"2019","unstructured":"Z. Zhu 2019 . A Configurable Multi-Precision CNN Computing Framework Based on Single Bit RRAM . In DAC , 2019. 1 -- 6 . Z. Zhu et al. 2019. A Configurable Multi-Precision CNN Computing Framework Based on Single Bit RRAM. In DAC, 2019. 1--6.","journal-title":"DAC"}],"event":{"name":"GLSVLSI '20: Great Lakes Symposium on VLSI 2020","location":"Virtual Event China","acronym":"GLSVLSI '20"},"container-title":["Proceedings of the 2020 on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3407647","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3386263.3407647","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:38:25Z","timestamp":1750199905000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386263.3407647"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,7]]},"references-count":22,"alternative-id":["10.1145\/3386263.3407647","10.1145\/3386263"],"URL":"https:\/\/doi.org\/10.1145\/3386263.3407647","relation":{},"subject":[],"published":{"date-parts":[[2020,9,7]]},"assertion":[{"value":"2020-09-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}