{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T19:16:58Z","timestamp":1772738218144,"version":"3.50.1"},"reference-count":106,"publisher":"Association for Computing Machinery (ACM)","issue":"HOPL","license":[{"start":{"date-parts":[[2020,6,12]],"date-time":"2020-06-12T00:00:00Z","timestamp":1591920000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Proc. ACM Program. Lang."],"published-print":{"date-parts":[[2020,6,14]]},"abstract":"<jats:p>This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog has completely revolutionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. For large-scale digital logic design, previous schematic-based techniques have transformed into textual register-transfer level (RTL) descriptions written in Verilog. As of 2018 about 80% of integrated circuit design teams worldwide use Verilog and its compatible descendant SystemVerilog.<\/jats:p>","DOI":"10.1145\/3386337","type":"journal-article","created":{"date-parts":[[2020,6,12]],"date-time":"2020-06-12T16:22:59Z","timestamp":1591978979000},"page":"1-90","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Verilog HDL and its ancestors and descendants"],"prefix":"10.1145","volume":"4","author":[{"given":"Peter","family":"Flake","sequence":"first","affiliation":[{"name":"Elda Technology, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Phil","family":"Moorby","sequence":"additional","affiliation":[{"name":"Rockport, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steve","family":"Golson","sequence":"additional","affiliation":[{"name":"Trilobyte Systems, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arturo","family":"Salz","sequence":"additional","affiliation":[{"name":"Synopsys, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Simon","family":"Davidmann","sequence":"additional","affiliation":[{"name":"Imperas Software, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,6,12]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Standard","author":"Accellera\u2019s SystemVerilog","unstructured":"Accellera. 2002a. SystemVerilog 3.0 Accellera\u2019s Extensions to Verilog . Standard . Accellera Organization , Napa, CA, USA . non-archival http:\/\/www.eda-twiki.org\/sv-ec\/3.0_LRM.pdf . Accellera. 2002a. SystemVerilog 3.0 Accellera\u2019s Extensions to Verilog. Standard. Accellera Organization, Napa, CA, USA. non-archival http:\/\/www.eda-twiki.org\/sv-ec\/3.0_LRM.pdf ."},{"key":"e_1_2_1_2_1","volume-title":"VHDL Users Group \/ VHDL International Users\u2019 Forum (VUG\/VIUF) Collected Conference Proceedings. Accellera. Archived at https:\/\/web.archive.org\/web\/20020803031109\/http:\/\/eda.org\/VIUF_proc\/ .","year":"2002","unstructured":"Accellera. 2002 b. VHDL Users Group \/ VHDL International Users\u2019 Forum (VUG\/VIUF) Collected Conference Proceedings. Accellera. Archived at https:\/\/web.archive.org\/web\/20020803031109\/http:\/\/eda.org\/VIUF_proc\/ . Accellera. 2002b. VHDL Users Group \/ VHDL International Users\u2019 Forum (VUG\/VIUF) Collected Conference Proceedings. Accellera. Archived at https:\/\/web.archive.org\/web\/20020803031109\/http:\/\/eda.org\/VIUF_proc\/ ."},{"key":"e_1_2_1_3_1","volume-title":"Accellera\u2019s Extensions to Verilog. Standard","author":"SystemVerilog","unstructured":"Accellera. 2003. SystemVerilog 3.1 , Accellera\u2019s Extensions to Verilog. Standard . Accellera Organization , Napa, CA, USA . non-archival http:\/\/www.eda-twiki.org\/sv-ec\/SystemVerilog_3.1_final.pdf (also at Internet Archive 7 April 2020 14:23:40 ). Accellera. 2003. SystemVerilog 3.1, Accellera\u2019s Extensions to Verilog. Standard. Accellera Organization, Napa, CA, USA. non-archival http:\/\/www.eda-twiki.org\/sv-ec\/SystemVerilog_3.1_final.pdf (also at Internet Archive 7 April 2020 14:23:40 )."},{"key":"e_1_2_1_4_1","volume-title":"Property Specification Language Reference Manual Version 1.1. Standard","year":"2004","unstructured":"Accellera. 2004a. Property Specification Language Reference Manual Version 1.1. Standard . Accellera Organization , Napa, CA, USA . Archived at https:\/\/web.archive.org\/web\/ 2004 0913230716\/http:\/\/www.eda.org\/vfv\/docs\/PSL-v1.1.pdf . Accellera. 2004a. Property Specification Language Reference Manual Version 1.1. Standard. Accellera Organization, Napa, CA, USA. Archived at https:\/\/web.archive.org\/web\/20040913230716\/http:\/\/www.eda.org\/vfv\/docs\/PSL-v1.1.pdf ."},{"key":"e_1_2_1_5_1","volume-title":"Accellera\u2019s Extensions to Verilog. Standard","author":"Language Reference Manual SystemVerilog","year":"2004","unstructured":"Accellera. 2004b. SystemVerilog 3.1a Language Reference Manual , Accellera\u2019s Extensions to Verilog. Standard . Accellera Organization , Napa, CA, USA . Archived at https:\/\/web.archive.org\/web\/ 2004 0626122728\/http:\/\/www.eda.org\/sv\/SystemVerilog_ 3.1a.pdf . Accellera. 2004b. SystemVerilog 3.1a Language Reference Manual, Accellera\u2019s Extensions to Verilog. Standard. Accellera Organization, Napa, CA, USA. Archived at https:\/\/web.archive.org\/web\/20040626122728\/http:\/\/www.eda.org\/sv\/SystemVerilog_ 3.1a.pdf ."},{"key":"e_1_2_1_6_1","volume-title":"Universal Verification Methodology (UVM) 1.0 Class Reference. Standard","unstructured":"Accellera. 2011. Universal Verification Methodology (UVM) 1.0 Class Reference. Standard . Accellera Organization , Napa, CA, USA . non-archival https:\/\/www.accellera.org\/images\/downloads\/standards\/uvm\/UVM_Class_Reference_Manual_1.0. pdf . Accellera. 2011. Universal Verification Methodology (UVM) 1.0 Class Reference. Standard. Accellera Organization, Napa, CA, USA. non-archival https:\/\/www.accellera.org\/images\/downloads\/standards\/uvm\/UVM_Class_Reference_Manual_1.0. pdf ."},{"key":"e_1_2_1_7_1","volume-title":"Verilog-AMS Language Reference Manual 2.4.0. Standard. Accellera Systems Initiative","unstructured":"Accellera. 2014. Verilog-AMS Language Reference Manual 2.4.0. Standard. Accellera Systems Initiative , Napa, CA, USA . non-archival https:\/\/www.accellera.org\/images\/downloads\/standards\/v-ams\/VAMS-LRM-2-4.pdf . Accellera. 2014. Verilog-AMS Language Reference Manual 2.4.0. Standard. Accellera Systems Initiative, Napa, CA, USA. non-archival https:\/\/www.accellera.org\/images\/downloads\/standards\/v-ams\/VAMS-LRM-2-4.pdf ."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-46002-0_21"},{"key":"e_1_2_1_9_1","volume-title":"The Java Programming Language","author":"Arnold Ken","unstructured":"Ken Arnold and James Gosling . 1998. The Java Programming Language ( second ed.). Addison-Wesley , New York, NY, USA . Ken Arnold and James Gosling. 1998. The Java Programming Language (second ed.). Addison-Wesley, New York, NY, USA."},{"key":"e_1_2_1_10_1","unstructured":"Peggy Aycinena. 2005. Phil Moorby - 2005 Kaufman Award. EDA Confidential (8 nov). Archived at https:\/\/web.archive.org\/ web\/20060325053055\/http:\/\/www.aycinena.com\/index2\/index3\/archive\/phil%20moorby.html . Ayciena gives a report on the awards dinner and includes an interview with Phil Moorby.  Peggy Aycinena. 2005. Phil Moorby - 2005 Kaufman Award. EDA Confidential (8 nov). Archived at https:\/\/web.archive.org\/ web\/20060325053055\/http:\/\/www.aycinena.com\/index2\/index3\/archive\/phil%20moorby.html . Ayciena gives a report on the awards dinner and includes an interview with Phil Moorby."},{"key":"e_1_2_1_11_1","volume-title":"IVC\/VIUF HDL Conference. OVI &amp; VI. Archived at https:\/\/web.archive.org\/web\/19980202191343\/http: \/\/www.hdlcon.org\/toppage.html .","author":"Baird Mike","year":"1998","unstructured":"Mike Baird . 1998 . IVC\/VIUF HDL Conference. OVI &amp; VI. Archived at https:\/\/web.archive.org\/web\/19980202191343\/http: \/\/www.hdlcon.org\/toppage.html . Mike Baird. 1998. IVC\/VIUF HDL Conference. OVI &amp; VI. Archived at https:\/\/web.archive.org\/web\/19980202191343\/http: \/\/www.hdlcon.org\/toppage.html ."},{"key":"e_1_2_1_12_1","volume-title":"The International HDL Conference and Exhibition. HDLCon. Archived at https:\/\/web.archive.org\/web\/ 19990208004605\/http:\/\/hdlcon.org\/ .","author":"Baird Mike","year":"1999","unstructured":"Mike Baird . 1999 . The International HDL Conference and Exhibition. HDLCon. Archived at https:\/\/web.archive.org\/web\/ 19990208004605\/http:\/\/hdlcon.org\/ . Mike Baird. 1999. The International HDL Conference and Exhibition. HDLCon. Archived at https:\/\/web.archive.org\/web\/ 19990208004605\/http:\/\/hdlcon.org\/ ."},{"key":"e_1_2_1_13_1","volume-title":"Digital computer fundamentals","author":"Bartee Thomas C.","year":"1960","unstructured":"Thomas C. Bartee . 1960. Digital computer fundamentals . McGraw-Hill , New York, NY, USA . The original 1960 edition is a classic early text on computer hardware. At the time, Bartee was at MIT Lincoln Laboratory. Thomas C. Bartee. 1960. Digital computer fundamentals. McGraw-Hill, New York, NY, USA. The original 1960 edition is a classic early text on computer hardware. At the time, Bartee was at MIT Lincoln Laboratory."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/647770.734116"},{"key":"e_1_2_1_15_1","volume-title":"Scan available at non-archival https: \/\/gordonbell.azurewebsites.net\/CGB%20Files\/High-Tech%20Ventures%201991%20c.pdf (also at Internet Archive","author":"Bell C. Gordon","year":"2020","unstructured":"C. Gordon Bell . 1991. High-Tech Ventures . Addison-Wesley, Reading, MA , USA. Scan available at non-archival https: \/\/gordonbell.azurewebsites.net\/CGB%20Files\/High-Tech%20Ventures%201991%20c.pdf (also at Internet Archive 31 March 2020 15:17:55 ). Pages 289\u2013299 discuss Gateway Design Automation . C. Gordon Bell. 1991. High-Tech Ventures. Addison-Wesley, Reading, MA, USA. Scan available at non-archival https: \/\/gordonbell.azurewebsites.net\/CGB%20Files\/High-Tech%20Ventures%201991%20c.pdf (also at Internet Archive 31 March 2020 15:17:55 ). Pages 289\u2013299 discuss Gateway Design Automation."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-010-1161-7"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1984.5005617"},{"key":"e_1_2_1_18_1","volume-title":"Verification Methodology Manual for SystemVerilog","author":"Bergeron Janick","unstructured":"Janick Bergeron , Eduard Cerny , Alan Hunter , and Andy Nightingale . 2005. Verification Methodology Manual for SystemVerilog . Springer-Verlag , Berlin, Heidelberg , Germany. Janick Bergeron, Eduard Cerny, Alan Hunter, and Andy Nightingale. 2005. Verification Methodology Manual for SystemVerilog. Springer-Verlag, Berlin, Heidelberg, Germany."},{"key":"e_1_2_1_19_1","first-page":"6","article-title":"Level-Sensitive Scan Design Tests Chips, Boards","volume":"52","author":"Berglund Neil C.","year":"1979","unstructured":"Neil C. Berglund . 1979 . Level-Sensitive Scan Design Tests Chips, Boards , System. Electronics 52 , 6 (March), 108\u2013110. Neil C. Berglund. 1979. Level-Sensitive Scan Design Tests Chips, Boards, System. Electronics 52, 6 (March), 108\u2013110.","journal-title":"System. Electronics"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.156158"},{"key":"e_1_2_1_21_1","volume-title":"Sangiovanni-Vincentelli","author":"Brayton Robert K.","year":"1984","unstructured":"Robert K. Brayton , Gary D. Hachtel , Curtis T. McMullen , and Alberto L . Sangiovanni-Vincentelli . 1984 . Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers , Boston, MA, USA. Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, and Alberto L. Sangiovanni-Vincentelli. 1984. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Boston, MA, USA."},{"key":"e_1_2_1_22_1","volume-title":"Cadence Design Systems","year":"2000","unstructured":"Cadence. 2000. TestBuilder. Cadence Design Systems , San Jose, CA, USA . Archived at https:\/\/web.archive.org\/web\/ 2000 1018010606\/http:\/\/www.testbuilder.net\/ . Cadence. 2000. TestBuilder. Cadence Design Systems, San Jose, CA, USA. Archived at https:\/\/web.archive.org\/web\/ 20001018010606\/http:\/\/www.testbuilder.net\/ ."},{"key":"e_1_2_1_23_1","unstructured":"Cadence and Mentor Graphics. 2008. Open Verification Methodology. Cadence and Mentor Graphics (9 Jan.). Archived at https:\/\/web.archive.org\/web\/20080115101515\/http:\/\/www.ovmworld.org\/ .  Cadence and Mentor Graphics. 2008. Open Verification Methodology. Cadence and Mentor Graphics (9 Jan.). Archived at https:\/\/web.archive.org\/web\/20080115101515\/http:\/\/www.ovmworld.org\/ ."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/6.214581"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228528"},{"key":"e_1_2_1_26_1","unstructured":"CHM. 2015. Computer History Museum Announces its 2016 Fellow Award Honorees. Computer History Museum (17 nov). Archived at https:\/\/web.archive.org\/web\/20200327134657\/https:\/\/computerhistory.org\/press-releases\/fellows-2016\/ .  CHM. 2015. Computer History Museum Announces its 2016 Fellow Award Honorees. Computer History Museum (17 nov). Archived at https:\/\/web.archive.org\/web\/20200327134657\/https:\/\/computerhistory.org\/press-releases\/fellows-2016\/ ."},{"key":"e_1_2_1_27_1","unstructured":"CHM. 2016. Philip Moorby. Computer History Museum. Archived at https:\/\/web.archive.org\/web\/20200331001046\/ https:\/\/computerhistory.org\/profile\/philip-moorby\/ . Video at https:\/\/www.youtube.com\/watch?v=pUmCdQVukrg . See earlier version at https:\/\/web.archive.org\/web\/20161003015054\/https:\/\/www.computerhistory.org\/fellowawards\/hall\/ Philip-Moorby\/ . Also see this page about the 2016 Fellow Awards https:\/\/web.archive.org\/web\/20191003110953\/https: \/\/computerhistory.org\/blog\/2016-chm-fellow-awards\/ .  CHM. 2016. Philip Moorby. Computer History Museum. Archived at https:\/\/web.archive.org\/web\/20200331001046\/ https:\/\/computerhistory.org\/profile\/philip-moorby\/ . Video at https:\/\/www.youtube.com\/watch?v=pUmCdQVukrg . See earlier version at https:\/\/web.archive.org\/web\/20161003015054\/https:\/\/www.computerhistory.org\/fellowawards\/hall\/ Philip-Moorby\/ . Also see this page about the 2016 Fellow Awards https:\/\/web.archive.org\/web\/20191003110953\/https: \/\/computerhistory.org\/blog\/2016-chm-fellow-awards\/ ."},{"key":"e_1_2_1_28_1","unstructured":"Peter Clarke. 1999. Startup to field next-generation design language. Electronic Engineering Times (1 June). Archived at https:\/\/web.archive.org\/web\/20001211142400\/http:\/\/www.edtn.com:80\/story\/tech\/OEG19990531S0003-R . An informative article that provides a very good summary of Co-Design and its vision for Superlog. Also mentions Co-Design\u2019s early investors.  Peter Clarke. 1999. Startup to field next-generation design language. Electronic Engineering Times (1 June). Archived at https:\/\/web.archive.org\/web\/20001211142400\/http:\/\/www.edtn.com:80\/story\/tech\/OEG19990531S0003-R . An informative article that provides a very good summary of Co-Design and its vision for Superlog. Also mentions Co-Design\u2019s early investors."},{"key":"e_1_2_1_29_1","unstructured":"Ronald Collett. 1993. VHDL by TKO. Electronic Engineering Times (4 Jan.) 42. Scan available at https:\/\/web.archive.org\/ web\/20200331183910\/https:\/\/trilobyte.com\/pdf\/VHDL_by_TKO_Collett_1993-01-04.pdf .  Ronald Collett. 1993. VHDL by TKO. Electronic Engineering Times (4 Jan.) 42. Scan available at https:\/\/web.archive.org\/ web\/20200331183910\/https:\/\/trilobyte.com\/pdf\/VHDL_by_TKO_Collett_1993-01-04.pdf ."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/800167.805400"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1049\/ir:20040803"},{"key":"e_1_2_1_32_1","unstructured":"Surrendra Dudani and Eduard Cerny. 2003. Authoring assertion IP using OpenVera assertion language. Design And Reuse (7 Feb.). https:\/\/www.design-reuse.com\/articles\/4835\/authoring-assertion-ip-using-openvera-assertion-language.html (also at Internet Archive 8 Sept. 2009 20:33:49 ).  Surrendra Dudani and Eduard Cerny. 2003. Authoring assertion IP using OpenVera assertion language. Design And Reuse (7 Feb.). https:\/\/www.design-reuse.com\/articles\/4835\/authoring-assertion-ip-using-openvera-assertion-language.html (also at Internet Archive 8 Sept. 2009 20:33:49 )."},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1968.229145"},{"key":"e_1_2_1_34_1","volume-title":"Phil Moorby Selected to Receive EDA Industry\u2019s Kaufman Award","author":"EDAC.","year":"2020","unstructured":"EDAC. 2005. Phil Moorby Selected to Receive EDA Industry\u2019s Kaufman Award . The EDA Consortium (10 oct). Archived at https:\/\/web.archive.org\/web\/ 2020 0330224958\/http:\/\/esd-alliance.org\/wp-content\/uploads\/PDFs\/PhilKaufmanAward\/ 05-10-10_PK_Award_FINAL.pdf . Press release from EDA Consortium . EDAC. 2005. Phil Moorby Selected to Receive EDA Industry\u2019s Kaufman Award. The EDA Consortium (10 oct). Archived at https:\/\/web.archive.org\/web\/20200330224958\/http:\/\/esd-alliance.org\/wp-content\/uploads\/PDFs\/PhilKaufmanAward\/ 05-10-10_PK_Award_FINAL.pdf . Press release from EDA Consortium."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.92.0090"},{"key":"e_1_2_1_36_1","volume-title":"Proceedings of the 14th Design Automation Conference","author":"Edward","year":"1977","unstructured":"Edward B. Eichelberger and Thomas W. Williams. 1977. A Logic Design Structure for LSI Testability . In Proceedings of the 14th Design Automation Conference ( New Orleans, LA, USA , 1977 -06-20\/1977-06-22) (DAC \u201977 ). IEEE Press, New York, NY, USA, 462\u2013468. Edward B. Eichelberger and Thomas W. Williams. 1977. A Logic Design Structure for LSI Testability. In Proceedings of the 14th Design Automation Conference (New Orleans, LA, USA, 1977-06-20\/1977-06-22) (DAC \u201977 ). IEEE Press, New York, NY, USA, 462\u2013468."},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-69850-0_8"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/368434.368814"},{"key":"e_1_2_1_39_1","volume-title":"Logic Simulation of Bi-directional Tri-state Gates. In IEEE International Conference on Circuits and Computers","author":"Flake Peter L.","year":"1980","unstructured":"Peter L. Flake , Philip R. Moorby , and Gerry Musgrave . 1980 . Logic Simulation of Bi-directional Tri-state Gates. In IEEE International Conference on Circuits and Computers ( Port Chester, NY, USA , 1980-10-01\/1980-10-03) (ICCC 80). IEEE, New York, NY, USA, 594\u2013600. Peter L. Flake, Philip R. Moorby, and Gerry Musgrave. 1980. Logic Simulation of Bi-directional Tri-state Gates. In IEEE International Conference on Circuits and Computers (Port Chester, NY, USA, 1980-10-01\/1980-10-03) (ICCC 80). IEEE, New York, NY, USA, 594\u2013600."},{"key":"e_1_2_1_40_1","volume-title":"HILO Mark 2 Hardware Description Language","author":"Flake Peter L.","year":"1981","unstructured":"Peter L. Flake , Philip R. Moorby , and Gerry Musgrave . 1981. HILO Mark 2 Hardware Description Language . In Computer Hardware Description Languages and Their Applications, Melvin A. Breuer and Reiner Hartenstein (Eds.). North-Holland, Amsterdam, Netherlands , 95\u2013108. This is Proceedings of the IFIP TC-10 Fifth International Conference on Computer Hardware Description Languages and Their Applications (Kaiserslautern, Germany) (CHDL \u201981), 7\u20139 Sep 1981 . Peter L. Flake, Philip R. Moorby, and Gerry Musgrave. 1981. HILO Mark 2 Hardware Description Language. In Computer Hardware Description Languages and Their Applications, Melvin A. Breuer and Reiner Hartenstein (Eds.). North-Holland, Amsterdam, Netherlands, 95\u2013108. This is Proceedings of the IFIP TC-10 Fifth International Conference on Computer Hardware Description Languages and Their Applications (Kaiserslautern, Germany) (CHDL \u201981), 7\u20139 Sep 1981."},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.5555\/800032.800733"},{"key":"e_1_2_1_42_1","volume-title":"International Symposium on Computer Hardware Description Languages and Their Applications","author":"Flake Peter L.","year":"1975","unstructured":"Peter L. Flake , Gerry Musgrave , and Mike Shorland . 1975 a. The HILO logic simulation language . In International Symposium on Computer Hardware Description Languages and Their Applications ( New York, NY, USA , 1975-09-03\/1975-09-05) (CHDL \u201975). IEEE, New York, NY, USA, 134\u2013142. IEEE catalog 75CH1010-8C. Peter L. Flake, Gerry Musgrave, and Mike Shorland. 1975a. The HILO logic simulation language. In International Symposium on Computer Hardware Description Languages and Their Applications (New York, NY, USA, 1975-09-03\/1975-09-05) (CHDL \u201975). IEEE, New York, NY, USA, 134\u2013142. IEEE catalog 75CH1010-8C."},{"key":"e_1_2_1_43_1","volume-title":"International Conference on Computer Aided Design","author":"Flake Peter L.","year":"1974","unstructured":"Peter L. Flake , Gerry Musgrave , and Ian J. White . 1974. HILO\u2014A Logic System Simulator . In International Conference on Computer Aided Design ( The University Of Southampton, UK , 1974 -04-08\/1974-04-11). Institution of Electrical Engineers, London, UK, 130\u2013136. IEE Conference Publication 111. Peter L. Flake, Gerry Musgrave, and Ian J. White. 1974. HILO\u2014A Logic System Simulator. In International Conference on Computer Aided Design (The University Of Southampton, UK, 1974-04-08\/1974-04-11). Institution of Electrical Engineers, London, UK, 130\u2013136. IEE Conference Publication 111."},{"key":"e_1_2_1_44_1","first-page":"39","article-title":"A Digital Systems Simulator\u2014HILO","volume":"1","author":"Flake Peter L.","year":"1975","unstructured":"Peter L. Flake , Gerry Musgrave , and Ian J. White . 1975 b. A Digital Systems Simulator\u2014HILO . Digital Processes 1 , 1, 39 \u2013 53 . Georgi Publishing Co. Peter L. Flake, Gerry Musgrave, and Ian J. White. 1975b. A Digital Systems Simulator\u2014HILO. Digital Processes 1, 1, 39\u201353. Georgi Publishing Co.","journal-title":"Digital Processes"},{"key":"e_1_2_1_45_1","unstructured":"FSF. 2000. Bison. Free Software Foundation. Archived at https:\/\/web.archive.org\/web\/20000831181346\/http:\/\/www.gnu.org\/ software\/bison\/ .  FSF. 2000. Bison. Free Software Foundation. Archived at https:\/\/web.archive.org\/web\/20000831181346\/http:\/\/www.gnu.org\/ software\/bison\/ ."},{"key":"e_1_2_1_46_1","volume-title":"The $8 Man, Brenda H","author":"Goel Prabhu","unstructured":"Prabhu Goel . 2017. Prabhu Goel , Silicon Valley . In The $8 Man, Brenda H . Christensen (Ed.). Redtop Publishing , Woodside, CA, USA , 51\u201376. Excerpt available at non-archival https:\/\/www.the8dollarman.com\/bios-8-men (also at Internet Archive 19 March 2019 14:29:36 ). Oral histories of Indian immigrants to the United States in 1960s\u20131970s. Prabhu Goel. 2017. Prabhu Goel, Silicon Valley. In The $8 Man, Brenda H. Christensen (Ed.). Redtop Publishing, Woodside, CA, USA, 51\u201376. Excerpt available at non-archival https:\/\/www.the8dollarman.com\/bios-8-men (also at Internet Archive 19 March 2019 14:29:36 ). Oral histories of Indian immigrants to the United States in 1960s\u20131970s."},{"key":"e_1_2_1_47_1","unstructured":"Richard Goering. 2005. Verilog\u2019s inventor nabs EDA\u2019s Kaufman award. Electronic Engineering Times (7 Nov.). nonarchival https:\/\/www.eetimes.com\/verilogs-inventor-nabs-edas-kaufman-award\/ . Also see this Usenet posting in comp.lang.verilog non-archival https:\/\/groups.google.com\/forum\/#!searchin\/comp.lang.verilog\/inventor\\protect\\T1\\ textdollar20nabs\\protect\\T1\\textdollar20kaufman\/comp.lang.verilog\/BND2Y24RSrI\/d7AwwvmrQW4J .  Richard Goering. 2005. Verilog\u2019s inventor nabs EDA\u2019s Kaufman award. Electronic Engineering Times (7 Nov.). nonarchival https:\/\/www.eetimes.com\/verilogs-inventor-nabs-edas-kaufman-award\/ . Also see this Usenet posting in comp.lang.verilog non-archival https:\/\/groups.google.com\/forum\/#!searchin\/comp.lang.verilog\/inventor\\protect\\T1\\ textdollar20nabs\\protect\\T1\\textdollar20kaufman\/comp.lang.verilog\/BND2Y24RSrI\/d7AwwvmrQW4J ."},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1016\/B978-0-408-01440-3.50012-4"},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1016\/0010-4485(84)90181-7"},{"key":"e_1_2_1_50_1","volume-title":"The History of CHDL Conferences. Archived at https:\/\/web.archive.org\/web\/20180829003543\/http: \/\/hartenstein.de\/CHDL\/","author":"Hartenstein Reiner","year":"2018","unstructured":"Reiner Hartenstein . 2018 . The History of CHDL Conferences. Archived at https:\/\/web.archive.org\/web\/20180829003543\/http: \/\/hartenstein.de\/CHDL\/ Reiner Hartenstein. 2018. The History of CHDL Conferences. Archived at https:\/\/web.archive.org\/web\/20180829003543\/http: \/\/hartenstein.de\/CHDL\/"},{"key":"e_1_2_1_51_1","unstructured":"Chi-lai Huang. 1981.\n  Computer-aided logic synthesis based on a new multi-level hardware design language\u2014LALSD II\n  . Ph.D. Dissertation. \n  State University of New York Binghamton NY USA\n  . Advisor(s) Stephen Y. H. Su. non-archival https:\/\/suny-bin.primo.exlibrisgroup.com\/permalink\/01SUNY_BIN\/1igql2k\/proquest303100438 .  Chi-lai Huang. 1981. Computer-aided logic synthesis based on a new multi-level hardware design language\u2014LALSD II. Ph.D. Dissertation. State University of New York Binghamton NY USA. Advisor(s) Stephen Y. H. Su. non-archival https:\/\/suny-bin.primo.exlibrisgroup.com\/permalink\/01SUNY_BIN\/1igql2k\/proquest303100438 ."},{"key":"e_1_2_1_52_1","volume-title":"Advanced UVM","author":"Hunter Brian","unstructured":"Brian Hunter . 2016. Advanced UVM ( second ed.). CreateSpace , Scotts Valley, CA, USA . Brian Hunter. 2016. Advanced UVM (second ed.). CreateSpace, Scotts Valley, CA, USA."},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1974.6323396"},{"key":"e_1_2_1_54_1","volume-title":"IEEE Standard VHDL Language Reference Manual","author":"IEEE","year":"1987","unstructured":"IEEE 1076-1987. IEEE Standard VHDL Language Reference Manual . IEEE, New York, NY, USA . https:\/\/standards.ieee.org\/ standard\/1076- 1987 .html . IEEE Std 1076-1987. IEEE 1076-1987. IEEE Standard VHDL Language Reference Manual. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/ standard\/1076-1987.html . IEEE Std 1076-1987."},{"key":"e_1_2_1_55_1","first-page":"1076","article-title":"IEEE Standard VHDL Language Reference Manual. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/ standard\/1076-1993.html","author":"IEEE","year":"1993","unstructured":"IEEE 1076- 1993 . IEEE Standard VHDL Language Reference Manual. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/ standard\/1076-1993.html . IEEE Std 1076 - 1993 . IEEE 1076-1993. IEEE Standard VHDL Language Reference Manual. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/ standard\/1076-1993.html . IEEE Std 1076-1993.","journal-title":"IEEE Std"},{"key":"e_1_2_1_56_1","first-page":"4","article-title":"IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/standard\/1076_4-1995.html","volume":"1076","author":"IEEE","year":"1995","unstructured":"IEEE 1076.4- 1995 . IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/standard\/1076_4-1995.html . IEEE Std 1076 . 4 - 1995 . IEEE 1076.4-1995. IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/standard\/1076_4-1995.html . IEEE Std 1076.4-1995.","journal-title":"IEEE Std"},{"key":"e_1_2_1_57_1","volume-title":"IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)","author":"IEEE","year":"1993","unstructured":"IEEE 1164-1993. IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) . IEEE, New York, NY, USA . http:\/\/standards.ieee.org\/standard\/1164- 1993 .html . IEEE Std 1164-1993. IEEE 1164-1993. IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164). IEEE, New York, NY, USA. http:\/\/standards.ieee.org\/standard\/1164-1993.html . IEEE Std 1164-1993."},{"key":"e_1_2_1_58_1","volume-title":"IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language","author":"IEEE","year":"1995","unstructured":"IEEE 1364-1995. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language . IEEE, New York, NY, USA . https:\/\/standards.ieee.org\/standard\/1364- 1995 .html . IEEE Std 1364-1995. IEEE 1364-1995. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/standard\/1364-1995.html . IEEE Std 1364-1995."},{"key":"e_1_2_1_59_1","volume-title":"IEEE Standard Verilog Hardware Description Language","author":"IEEE","year":"2001","unstructured":"IEEE 1364-2001. IEEE Standard Verilog Hardware Description Language . IEEE, New York, NY, USA . https:\/\/standards.ieee. org\/standard\/1364- 2001 .html . IEEE Std 1364-2001. IEEE 1364-2001. IEEE Standard Verilog Hardware Description Language. IEEE, New York, NY, USA. https:\/\/standards.ieee. org\/standard\/1364-2001.html . IEEE Std 1364-2001."},{"key":"e_1_2_1_60_1","first-page":"1","article-title":"IEEE Standard for Verilog Register Transfer Level Synthesis. IEEE, New York, NY, USA. https:\/\/standards. ieee.org\/standard\/1364_1-2002.html","volume":"1364","author":"IEEE","year":"2002","unstructured":"IEEE 1364- 2002 . IEEE Standard for Verilog Register Transfer Level Synthesis. IEEE, New York, NY, USA. https:\/\/standards. ieee.org\/standard\/1364_1-2002.html . IEEE Std 1364 . 1 - 2002 . IEEE 1364-2002. IEEE Standard for Verilog Register Transfer Level Synthesis. IEEE, New York, NY, USA. https:\/\/standards. ieee.org\/standard\/1364_1-2002.html . IEEE Std 1364.1-2002.","journal-title":"IEEE Std"},{"key":"e_1_2_1_61_1","volume-title":"IEEE Standard Verilog Hardware Description Language","author":"IEEE","year":"2005","unstructured":"IEEE 1364-2005. IEEE Standard Verilog Hardware Description Language . IEEE, New York, NY, USA . https:\/\/standards.ieee. org\/standard\/1364- 2005 .html . IEEE Std 1364-2005. IEEE 1364-2005. IEEE Standard Verilog Hardware Description Language. IEEE, New York, NY, USA. https:\/\/standards.ieee. org\/standard\/1364-2005.html . IEEE Std 1364-2005."},{"key":"e_1_2_1_62_1","first-page":"1497","article-title":"IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/standard\/1497-2001.html","author":"IEEE","year":"2001","unstructured":"IEEE 1497- 2001 . IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/standard\/1497-2001.html . IEEE Std 1497 - 2001 . IEEE 1497-2001. IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/standard\/1497-2001.html . IEEE Std 1497-2001.","journal-title":"IEEE Std"},{"key":"e_1_2_1_63_1","first-page":"1647","article-title":"IEEE Standard for the Functional Verification Language \u2018e\u2019. IEEE, New York, NY, USA. https:\/\/standards.ieee. org\/standard\/1647-2006.html","author":"IEEE","year":"2006","unstructured":"IEEE 1647- 2006 . IEEE Standard for the Functional Verification Language \u2018e\u2019. IEEE, New York, NY, USA. https:\/\/standards.ieee. org\/standard\/1647-2006.html . IEEE Std 1647 - 2006 . IEEE 1647-2006. IEEE Standard for the Functional Verification Language \u2018e\u2019. IEEE, New York, NY, USA. https:\/\/standards.ieee. org\/standard\/1647-2006.html . IEEE Std 1647-2006.","journal-title":"IEEE Std"},{"key":"e_1_2_1_64_1","volume-title":"IEEE Standard for Standard SystemC Language Reference Manual","author":"IEEE","year":"2011","unstructured":"IEEE 1666- 2011. IEEE Standard for Standard SystemC Language Reference Manual . IEEE, New York, NY, USA . http: \/\/standards.ieee.org\/standard\/1666- 2011 .html . IEEE Std 1666-2011. IEEE 1666- 2011. IEEE Standard for Standard SystemC Language Reference Manual. IEEE, New York, NY, USA. http: \/\/standards.ieee.org\/standard\/1666-2011.html . IEEE Std 1666-2011."},{"key":"e_1_2_1_65_1","volume-title":"IEEE Standard for SystemVerilog\u2014Unified Hardware Design, Specification, and Verification Language","author":"IEEE","year":"1800","unstructured":"IEEE 1800-2005. IEEE Standard for SystemVerilog\u2014Unified Hardware Design, Specification, and Verification Language . IEEE, New York, NY, USA . http:\/\/standards.ieee.org\/standard\/ 1800 -2005.html . IEEE Std 1800-2005. IEEE 1800-2005. IEEE Standard for SystemVerilog\u2014Unified Hardware Design, Specification, and Verification Language. IEEE, New York, NY, USA. http:\/\/standards.ieee.org\/standard\/1800-2005.html . IEEE Std 1800-2005."},{"key":"e_1_2_1_66_1","first-page":"1800","article-title":"-2009. IEEE Standard for SystemVerilog\u2014Unified Hardware Design, Specification, and Verification Language. IEEE, New York, NY, USA. http:\/\/standards.ieee.org\/standard\/1800-2009.html","author":"IEEE","year":"1800","unstructured":"IEEE 1800 -2009. IEEE Standard for SystemVerilog\u2014Unified Hardware Design, Specification, and Verification Language. IEEE, New York, NY, USA. http:\/\/standards.ieee.org\/standard\/1800-2009.html . IEEE Std 1800 - 2009 . IEEE 1800-2009. IEEE Standard for SystemVerilog\u2014Unified Hardware Design, Specification, and Verification Language. IEEE, New York, NY, USA. http:\/\/standards.ieee.org\/standard\/1800-2009.html . IEEE Std 1800-2009.","journal-title":"IEEE Std"},{"key":"e_1_2_1_67_1","volume-title":"IEEE Standard for SystemVerilog\u2014Unified Hardware Design, Specification, and Verification Language","author":"IEEE","year":"1800","unstructured":"IEEE 1800-2012. IEEE Standard for SystemVerilog\u2014Unified Hardware Design, Specification, and Verification Language . IEEE, New York, NY, USA . http:\/\/standards.ieee.org\/standard\/ 1800 -2012.html . IEEE Std 1800-2012. IEEE 1800-2012. IEEE Standard for SystemVerilog\u2014Unified Hardware Design, Specification, and Verification Language. IEEE, New York, NY, USA. http:\/\/standards.ieee.org\/standard\/1800-2012.html . IEEE Std 1800-2012."},{"key":"e_1_2_1_68_1","volume-title":"IEEE Standard for SystemVerilog\u2014Unified Hardware Design, Specification, and Verification Language","author":"IEEE","year":"1800","unstructured":"IEEE 1800-2017. IEEE Standard for SystemVerilog\u2014Unified Hardware Design, Specification, and Verification Language . IEEE, New York, NY, USA . http:\/\/standards.ieee.org\/standard\/ 1800 -2017.html . IEEE Std 1800-2017. IEEE 1800-2017. IEEE Standard for SystemVerilog\u2014Unified Hardware Design, Specification, and Verification Language. IEEE, New York, NY, USA. http:\/\/standards.ieee.org\/standard\/1800-2017.html . IEEE Std 1800-2017."},{"key":"e_1_2_1_69_1","first-page":"2","article-title":"2-2017. IEEE Standard for Universal Verification Methodology Language Reference Manual. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/standard\/1800_2-2017.html","volume":"1800","author":"IEEE","year":"1800","unstructured":"IEEE 1800 . 2-2017. IEEE Standard for Universal Verification Methodology Language Reference Manual. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/standard\/1800_2-2017.html . IEEE Std 1800 . 2 - 2017 . IEEE 1800.2-2017. IEEE Standard for Universal Verification Methodology Language Reference Manual. IEEE, New York, NY, USA. https:\/\/standards.ieee.org\/standard\/1800_2-2017.html . IEEE Std 1800.2-2017.","journal-title":"IEEE Std"},{"key":"e_1_2_1_70_1","first-page":"1850","article-title":"-2005. IEEE Standard for Property Specification Language (PSL). IEEE, New York, NY, USA. http:\/\/standards.ieee. org\/standard\/1850-2005.html","author":"IEEE","year":"1850","unstructured":"IEEE 1850 -2005. IEEE Standard for Property Specification Language (PSL). IEEE, New York, NY, USA. http:\/\/standards.ieee. org\/standard\/1850-2005.html . IEEE Std 1850 - 2005 . IEEE 1850-2005. IEEE Standard for Property Specification Language (PSL). IEEE, New York, NY, USA. http:\/\/standards.ieee. org\/standard\/1850-2005.html . IEEE Std 1850-2005.","journal-title":"IEEE Std"},{"key":"e_1_2_1_71_1","volume-title":"IEEE Standard for Property Specification Language (PSL)","author":"IEEE","year":"1850","unstructured":"IEEE 1850-2010. IEEE Standard for Property Specification Language (PSL) . IEEE, New York, NY, USA . http:\/\/standards.ieee. org\/standard\/ 1850 -2010.html . IEEE Std 1850-2010. IEEE 1850-2010. IEEE Standard for Property Specification Language (PSL). IEEE, New York, NY, USA. http:\/\/standards.ieee. org\/standard\/1850-2010.html . IEEE Std 1850-2010."},{"key":"e_1_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1007\/b117092"},{"key":"e_1_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.1109\/6.214581"},{"key":"e_1_2_1_75_1","unstructured":"Harvey Jones. 2009. Oral History of Harvey Jones. Computer History Museum (6 Nov.). http:\/\/www.computerhistory.org\/ collections\/catalog\/102702217 (also at Internet Archive 3 Oct. 2013 02:33:32 ). Catalog number 102702217.  Harvey Jones. 2009. Oral History of Harvey Jones. Computer History Museum (6 Nov.). http:\/\/www.computerhistory.org\/ collections\/catalog\/102702217 (also at Internet Archive 3 Oct. 2013 02:33:32 ). Catalog number 102702217."},{"key":"e_1_2_1_76_1","doi-asserted-by":"publisher","DOI":"10.1145\/800123.803968"},{"key":"e_1_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0053381"},{"key":"e_1_2_1_78_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1987.295189"},{"key":"e_1_2_1_79_1","first-page":"170","article-title":"O logice tr\u00f3jwarto\u015bciowej","volume":"5","author":"\u0141ukasiewicz Jan","year":"1920","unstructured":"Jan \u0141ukasiewicz . 1920 . O logice tr\u00f3jwarto\u015bciowej . Ruch Filozoficzny 5 , 170 \u2013 171 . Translation: On three-valued logic. Also see: Peter Simons. 2017. Jan \u0141ukasiewicz. In The Stanford Encyclopedia of Philosophy (spring 2017 ed.), Edward N. Zalta (Ed.). Metaphysics Research Lab, Stanford University. Archived at https:\/\/plato.stanford.edu\/archives\/spr2017\/entries\/ lukasiewicz\/ . Jan \u0141ukasiewicz. 1920. O logice tr\u00f3jwarto\u015bciowej. Ruch Filozoficzny 5, 170\u2013171. Translation: On three-valued logic. Also see: Peter Simons. 2017. Jan \u0141ukasiewicz. In The Stanford Encyclopedia of Philosophy (spring 2017 ed.), Edward N. Zalta (Ed.). Metaphysics Research Lab, Stanford University. Archived at https:\/\/plato.stanford.edu\/archives\/spr2017\/entries\/ lukasiewicz\/ .","journal-title":"Ruch Filozoficzny"},{"key":"e_1_2_1_80_1","unstructured":"Rajeev Madhavan. 1997. About IVC. OVI. Archived at https:\/\/web.archive.org\/web\/19970414023820\/http:\/\/www.hdlcon. org\/aboutivc.html .  Rajeev Madhavan. 1997. About IVC. OVI. Archived at https:\/\/web.archive.org\/web\/19970414023820\/http:\/\/www.hdlcon. org\/aboutivc.html ."},{"key":"e_1_2_1_81_1","volume-title":"Mentor Graphics Delivers the Next Generation of Functional Verification. Mentor Graphics","author":"Graphics Mentor","year":"2010","unstructured":"Mentor Graphics . 2006. Mentor Graphics Delivers the Next Generation of Functional Verification. Mentor Graphics , Inc. (6 may). Archived at https:\/\/web.archive.org\/web\/ 2010 0523143319\/https:\/\/www.mentor.com\/company\/news\/questa_avm . Mentor Graphics. 2006. Mentor Graphics Delivers the Next Generation of Functional Verification. Mentor Graphics, Inc. (6 may). Archived at https:\/\/web.archive.org\/web\/20100523143319\/https:\/\/www.mentor.com\/company\/news\/questa_avm ."},{"key":"e_1_2_1_82_1","volume-title":"Standard General Requirements for Electronic Equipment. US Department of Defense","author":"L.","unstructured":"MIL-STD-454 L. 1988. Standard General Requirements for Electronic Equipment. US Department of Defense , Washington, DC, USA (20 Sep) . MIL-STD-454L. 1988. Standard General Requirements for Electronic Equipment. US Department of Defense, Washington, DC, USA (20 Sep)."},{"key":"e_1_2_1_83_1","volume-title":"RTL Coding Styles That Yield Simulation and Synthesis Mismatches. In Synopsys Users Group Conference","author":"Mills Don","year":"1999","unstructured":"Don Mills and Clifford E. Cummings . 1999 . RTL Coding Styles That Yield Simulation and Synthesis Mismatches. In Synopsys Users Group Conference ( San Jose, CA, USA , 1999 -03-29\/1999-03-30) (SNUG San Jose 1999). Synopsys, Mountain View, CA, USA, 1\u201316. non-archival http:\/\/www.sunburst-design.com\/papers\/CummingsSNUG1999SJ_SynthMismatch.pdf (also at Internet Archive 12 Jan. 2006 04:11:53 ). Don Mills and Clifford E. Cummings. 1999. RTL Coding Styles That Yield Simulation and Synthesis Mismatches. In Synopsys Users Group Conference (San Jose, CA, USA, 1999-03-29\/1999-03-30) (SNUG San Jose 1999). Synopsys, Mountain View, CA, USA, 1\u201316. non-archival http:\/\/www.sunburst-design.com\/papers\/CummingsSNUG1999SJ_SynthMismatch.pdf (also at Internet Archive 12 Jan. 2006 04:11:53 )."},{"key":"e_1_2_1_84_1","volume-title":"Moorby. Computer History Museum (22 April). https: \/\/www.computerhistory.org\/collections\/catalog\/102746653 (also at Internet Archive","author":"Moorby Philip","year":"2014","unstructured":"Philip Moorby . 2013. Oral History of Philip Raymond \u201cPhil \u201d Moorby. Computer History Museum (22 April). https: \/\/www.computerhistory.org\/collections\/catalog\/102746653 (also at Internet Archive 4 Jan. 2014 12:35:24 ). Catalog number 102746653. Philip Moorby. 2013. Oral History of Philip Raymond \u201cPhil\u201d Moorby. Computer History Museum (22 April). https: \/\/www.computerhistory.org\/collections\/catalog\/102746653 (also at Internet Archive 4 Jan. 2014 12:35:24 ). Catalog number 102746653."},{"key":"e_1_2_1_85_1","volume-title":"Design and Verification Conference","author":"Moorby Phil","year":"2003","unstructured":"Phil Moorby , Arturo Salz , Peter Flake , Surrendra Dudani , and Tom Fitzpatrick . 2003 . Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics . In Design and Verification Conference ( San Jose, CA, USA , 2003-02-24\/2003-02-25) (DVCon 2003). Accellera, Napa, CA, USA, 1\u20137. Archived at Phil Moorby, Arturo Salz, Peter Flake, Surrendra Dudani, and Tom Fitzpatrick. 2003. Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics. In Design and Verification Conference (San Jose, CA, USA, 2003-02-24\/2003-02-25) (DVCon 2003). Accellera, Napa, CA, USA, 1\u20137. Archived at"},{"key":"e_1_2_1_86_1","volume-title":"IEEE International Conference on Computer-Aided Design","author":"Moorby Philip R.","year":"1983","unstructured":"Philip R. Moorby . 1983 . Fault Simulation using Parallel Value Lists . In IEEE International Conference on Computer-Aided Design ( Santa Clara, CA, USA , 1983-09-12\/1983-09-15) (ICCAD \u201983). IEEE, New York, NY, USA, 101\u2013102. Philip R. Moorby. 1983. Fault Simulation using Parallel Value Lists. In IEEE International Conference on Computer-Aided Design (Santa Clara, CA, USA, 1983-09-12\/1983-09-15) (ICCAD \u201983). IEEE, New York, NY, USA, 101\u2013102."},{"key":"e_1_2_1_87_1","unstructured":"Gabe Moretti. 2015. DVCon is the Primary Design and Verification Conference. Chip Design Magazine (20 Feb.). Archived at https:\/\/web.archive.org\/web\/20150304150425\/http:\/\/chipdesignmag.com\/sld\/moretti\/2015\/02\/20\/dvcon-is-the-primarydesign-and-verification-conference .  Gabe Moretti. 2015. DVCon is the Primary Design and Verification Conference. Chip Design Magazine (20 Feb.). Archived at https:\/\/web.archive.org\/web\/20150304150425\/http:\/\/chipdesignmag.com\/sld\/moretti\/2015\/02\/20\/dvcon-is-the-primarydesign-and-verification-conference ."},{"key":"e_1_2_1_88_1","volume-title":"Fabless: The Transformation of the Semiconductor Industry. SemiWiki.com, USA. non-archival https:\/\/semiwiki.com\/forum\/images\/BookCovers\/Fabless%202019%20Version%20PDF.pdf (also at Internet Archive","author":"Nenni Daniel","year":"2019","unstructured":"Daniel Nenni and Paul McLellan . 2019 . Fabless: The Transformation of the Semiconductor Industry. SemiWiki.com, USA. non-archival https:\/\/semiwiki.com\/forum\/images\/BookCovers\/Fabless%202019%20Version%20PDF.pdf (also at Internet Archive 5 Nov. 2019 22:05:09 ). Daniel Nenni and Paul McLellan. 2019. Fabless: The Transformation of the Semiconductor Industry. SemiWiki.com, USA. non-archival https:\/\/semiwiki.com\/forum\/images\/BookCovers\/Fabless%202019%20Version%20PDF.pdf (also at Internet Archive 5 Nov. 2019 22:05:09 )."},{"key":"e_1_2_1_89_1","volume-title":"Presentation of the 2005 Phil Kaufman Award to Phil Moorby","author":"Newton A. Richard","year":"2020","unstructured":"A. Richard Newton . 2005. Presentation of the 2005 Phil Kaufman Award to Phil Moorby . University of California , Berkeley, CA, USA (1 nov). Archived at https:\/\/web.archive.org\/web\/ 2020 0330233003\/https:\/\/people.eecs.berkeley.edu\/~newton\/ Presentations\/Kaufman\/PMPresent.html . Richard Newton\u2019s speech introducing Moorby at the awards ceremony. A. Richard Newton. 2005. Presentation of the 2005 Phil Kaufman Award to Phil Moorby. University of California, Berkeley, CA, USA (1 nov). Archived at https:\/\/web.archive.org\/web\/20200330233003\/https:\/\/people.eecs.berkeley.edu\/~newton\/ Presentations\/Kaufman\/PMPresent.html . Richard Newton\u2019s speech introducing Moorby at the awards ceremony."},{"key":"e_1_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1145\/1862876.1862877"},{"key":"e_1_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.1145\/800259.809004"},{"key":"e_1_2_1_92_1","volume-title":"The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology","author":"Salemi Ray","unstructured":"Ray Salemi . 2013. The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology . Boston Light Press, Boston, MA , USA. Ray Salemi. 2013. The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology. Boston Light Press, Boston, MA, USA."},{"key":"e_1_2_1_93_1","volume-title":"Synopsys Users Group Conference","author":"Salz Arturo","year":"2012","unstructured":"Arturo Salz , Bruce Greene , and Robert Booth . 2012 . X-Optimism Elimination during RTL Verification . In Synopsys Users Group Conference ( Santa Clara, CA, USA , 2012-03-26\/2012-03-28) (SNUG Silicon Valley 2012). Synopsys, Mountain View, CA, USA, 1\u201316. Archived at https:\/\/web.archive.org\/web\/20200331183948\/https:\/\/trilobyte.com\/pdf\/x-optimism_elimination_ SNUG_2012.pdf . Arturo Salz, Bruce Greene, and Robert Booth. 2012. X-Optimism Elimination during RTL Verification. In Synopsys Users Group Conference (Santa Clara, CA, USA, 2012-03-26\/2012-03-28) (SNUG Silicon Valley 2012). Synopsys, Mountain View, CA, USA, 1\u201316. Archived at https:\/\/web.archive.org\/web\/20200331183948\/https:\/\/trilobyte.com\/pdf\/x-optimism_elimination_ SNUG_2012.pdf ."},{"key":"e_1_2_1_94_1","volume-title":"Dept. of Electrical Engineering","author":"Shannon Claude Elwood","unstructured":"Claude Elwood Shannon . 1940. A symbolic analysis of relay and switching circuits. Master\u2019s thesis. MIT , Dept. of Electrical Engineering , Cambridge, MA , USA. Archived at http:\/\/hdl.handle.net\/1721.1\/11173 . Claude Elwood Shannon. 1940. A symbolic analysis of relay and switching circuits. Master\u2019s thesis. MIT, Dept. of Electrical Engineering, Cambridge, MA, USA. Archived at http:\/\/hdl.handle.net\/1721.1\/11173 ."},{"key":"e_1_2_1_95_1","volume-title":"Application-specific integrated circuits","author":"Sebastian Smith Michael John","unstructured":"Michael John Sebastian Smith . 1993. Application-specific integrated circuits . Addison-Wesley, Reading, MA , USA. Archived at https:\/\/archive.org\/details\/ApplicationSpecificIntegratedCircuitsAddisonWesleyMichaelJohnSebastianSmith\/mode\/ 2up . Michael John Sebastian Smith. 1993. Application-specific integrated circuits. Addison-Wesley, Reading, MA, USA. Archived at https:\/\/archive.org\/details\/ApplicationSpecificIntegratedCircuitsAddisonWesleyMichaelJohnSebastianSmith\/mode\/ 2up ."},{"key":"e_1_2_1_96_1","volume-title":"Why You Need It. In 9th Annual International HDL Conference and Exhibition","author":"Sutherland Stuart","year":"2000","unstructured":"Stuart Sutherland . 2000 . The IEEE Verilog 1364-2001 Standard: What\u2019s New, and Why You Need It. In 9th Annual International HDL Conference and Exhibition ( San Jose, CA, USA , 2000-03-08\/2000-03-10) (HDLCon \u201900). OVI &amp; VI, USA, 1\u20138. Archived at https:\/\/web.archive.org\/web\/20030403025314\/https:\/\/sutherland-hdl.com\/papers\/2000-HDLConpaper_Verilog-2000.pdf . Slides at https:\/\/web.archive.org\/web\/20030403102459\/https:\/\/sutherland-hdl.com\/papers\/2000-HDLCon-presentation_Verilog-2000.pdf . Stuart Sutherland. 2000. The IEEE Verilog 1364-2001 Standard: What\u2019s New, and Why You Need It. In 9th Annual International HDL Conference and Exhibition (San Jose, CA, USA, 2000-03-08\/2000-03-10) (HDLCon \u201900). OVI &amp; VI, USA, 1\u20138. Archived at https:\/\/web.archive.org\/web\/20030403025314\/https:\/\/sutherland-hdl.com\/papers\/2000-HDLConpaper_Verilog-2000.pdf . Slides at https:\/\/web.archive.org\/web\/20030403102459\/https:\/\/sutherland-hdl.com\/papers\/2000-HDLCon-presentation_Verilog-2000.pdf ."},{"key":"e_1_2_1_97_1","volume-title":"RTL Modeling With SystemVerilog for Simulation and Synthesis. Sutherland HDL","author":"Sutherland Stuart","unstructured":"Stuart Sutherland . 2017. RTL Modeling With SystemVerilog for Simulation and Synthesis. Sutherland HDL , Tualatin, OR, USA . Stuart Sutherland. 2017. RTL Modeling With SystemVerilog for Simulation and Synthesis. Sutherland HDL, Tualatin, OR, USA."},{"key":"e_1_2_1_98_1","doi-asserted-by":"publisher","DOI":"10.1007\/0-387-36495-1"},{"key":"e_1_2_1_99_1","volume-title":"The Verilog Hardware Description Language","author":"Thomas Donald","unstructured":"Donald Thomas and Philip Moorby . 1991. The Verilog Hardware Description Language . Kluwer Academic Publishers , Dordrecht, Netherlands . This book is the first public description of the Verilog language. There have been five editions: 1991, 1995, 1996, 1998, and 2002. The second edition included a DOS diskette containing examples from the book and a Verilog simulator. The third through fifth editions included a CD-ROM with examples and a simulator. Donald Thomas and Philip Moorby. 1991. The Verilog Hardware Description Language. Kluwer Academic Publishers, Dordrecht, Netherlands. This book is the first public description of the Verilog language. There have been five editions: 1991, 1995, 1996, 1998, and 2002. The second edition included a DOS diskette containing examples from the book and a Verilog simulator. The third through fifth editions included a CD-ROM with examples and a simulator."},{"key":"e_1_2_1_100_1","volume-title":"The Verilog Hardware Description Language","author":"Thomas Donald","unstructured":"Donald Thomas and Philip Moorby . 1995. The Verilog Hardware Description Language ( second ed.). Kluwer Academic Publishers, Dordrecht , Netherlands . The Foreward by C. Gordon Bell gives a nice summary of the Verilog market as of 1995. Donald Thomas and Philip Moorby. 1995. The Verilog Hardware Description Language (second ed.). Kluwer Academic Publishers, Dordrecht, Netherlands. The Foreward by C. Gordon Bell gives a nice summary of the Verilog market as of 1995."},{"key":"e_1_2_1_101_1","volume-title":"Synopsys Users Group Conference","author":"Turpin Mike","year":"2003","unstructured":"Mike Turpin . 2003 . The Dangers of Living with an X (bugs hidden in your Verilog) . In Synopsys Users Group Conference ( San Jose, CA, USA , 2003-03-17\/2003-03-19) (SNUG San Jose 2003). Synopsys, Mountain View, CA, USA, 1\u201334. Archived at https:\/\/web.archive.org\/web\/20150510162606\/http:\/\/infocenter.arm.com\/help\/topic\/com.arm.doc.arp0009a\/Verilog_ X_Bugs.pdf . Mike Turpin. 2003. The Dangers of Living with an X (bugs hidden in your Verilog). In Synopsys Users Group Conference (San Jose, CA, USA, 2003-03-17\/2003-03-19) (SNUG San Jose 2003). Synopsys, Mountain View, CA, USA, 1\u201334. Archived at https:\/\/web.archive.org\/web\/20150510162606\/http:\/\/infocenter.arm.com\/help\/topic\/com.arm.doc.arp0009a\/Verilog_ X_Bugs.pdf ."},{"key":"e_1_2_1_102_1","doi-asserted-by":"publisher","DOI":"10.1145\/362848.362870"},{"key":"e_1_2_1_103_1","volume-title":"Canada, 1995-08-27\/1995-09-03) (VIII Banff Higher Order Workshop). Springer-Verlag","author":"Vardi Moshe Y.","year":"1995","unstructured":"Moshe Y. Vardi . 1995 . An Automata-Theoretic Approach to Linear Temporal Logic. In Logics for Concurrency : Structure versus Automata (Banff , Canada, 1995-08-27\/1995-09-03) (VIII Banff Higher Order Workshop). Springer-Verlag , Berlin, Heidelberg, Germany, 238\u2013266. Moshe Y. Vardi. 1995. An Automata-Theoretic Approach to Linear Temporal Logic. In Logics for Concurrency : Structure versus Automata (Banff, Canada, 1995-08-27\/1995-09-03) (VIII Banff Higher Order Workshop). Springer-Verlag, Berlin, Heidelberg, Germany, 238\u2013266."},{"key":"e_1_2_1_104_1","unstructured":"Srivatsa Vasudevan. 2016. Practical UVM. CreateSpace Scotts Valley CA USA.  Srivatsa Vasudevan. 2016. Practical UVM. CreateSpace Scotts Valley CA USA."},{"key":"e_1_2_1_105_1","unstructured":"Verisity Design. 2002. eRM : e Reuse Methodology. Verisity Design. Archived at https:\/\/web.archive.org\/web\/20021009225113\/ http:\/\/www.verisity.com\/products\/erm.html .  Verisity Design. 2002. eRM : e Reuse Methodology. Verisity Design. Archived at https:\/\/web.archive.org\/web\/20021009225113\/ http:\/\/www.verisity.com\/products\/erm.html ."},{"key":"e_1_2_1_106_1","unstructured":"Frank Weiler. 2003. DVCon. Accellera Napa CA USA. Archived at https:\/\/web.archive.org\/web\/20030408023416\/http: \/\/www.hdlcon.org\/geninfo.html .  Frank Weiler. 2003. DVCon. Accellera Napa CA USA. Archived at https:\/\/web.archive.org\/web\/20030408023416\/http: \/\/www.hdlcon.org\/geninfo.html ."},{"key":"e_1_2_1_108_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.310057"}],"container-title":["Proceedings of the ACM on Programming Languages"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386337","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3386337","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:32:04Z","timestamp":1750195924000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3386337"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,6,12]]},"references-count":106,"journal-issue":{"issue":"HOPL","published-print":{"date-parts":[[2020,6,14]]}},"alternative-id":["10.1145\/3386337"],"URL":"https:\/\/doi.org\/10.1145\/3386337","relation":{},"ISSN":["2475-1421"],"issn-type":[{"value":"2475-1421","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,6,12]]},"assertion":[{"value":"2020-06-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}