{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,4]],"date-time":"2025-07-04T06:15:33Z","timestamp":1751609733486,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,1,18]],"date-time":"2021-01-18T00:00:00Z","timestamp":1610928000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Key Research and Development Program of China","award":["2020YFA0711901"],"award-info":[{"award-number":["2020YFA0711901"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,1,18]]},"DOI":"10.1145\/3394885.3431543","type":"proceedings-article","created":{"date-parts":[[2021,1,29]],"date-time":"2021-01-29T11:32:46Z","timestamp":1611919966000},"page":"146-151","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization"],"prefix":"10.1145","author":[{"given":"Jiangli","family":"Huang","sequence":"first","affiliation":[{"name":"State Key Lab of ASIC System, School of Microelectronics, Fudan University, China"}]},{"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"State Key Lab of ASIC System, School of Microelectronics, Fudan University, China"}]},{"given":"Changhao","family":"Yan","sequence":"additional","affiliation":[{"name":"State Key Lab of ASIC System, School of Microelectronics, Fudan University, China"}]},{"given":"Dian","family":"Zhou","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, U.S.A"}]},{"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"State Key Lab of ASIC System, School of Microelectronics, Fudan University, China"}]}],"member":"320","published-online":{"date-parts":[[2021,1,29]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.889371"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.810742"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593131"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11081-007-9001-7"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167553"},{"key":"e_1_3_2_1_6_1","volume-title":"Analog circuit sizing via swarm intelligence. AEU-International journal of electronics and communications, 66(9):732--740","author":"Vural RA","year":"2012","unstructured":"RA Vural and T Yildirim . Analog circuit sizing via swarm intelligence. AEU-International journal of electronics and communications, 66(9):732--740 , 2012 . RA Vural and T Yildirim. Analog circuit sizing via swarm intelligence. AEU-International journal of electronics and communications, 66(9):732--740, 2012."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.848091"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.04.003"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2494218"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2768826"},{"key":"e_1_3_2_1_11_1","volume-title":"Gaussian processes for machine learning","author":"Williams Christopher KI","year":"2006","unstructured":"Christopher KI Williams and Carl Edward Rasmussen . Gaussian processes for machine learning , volume 2 . MIT press Cambridge , MA , 2006 . Christopher KI Williams and Carl Edward Rasmussen. Gaussian processes for machine learning, volume 2. MIT press Cambridge, MA, 2006."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/3157382.3157448"},{"key":"e_1_3_2_1_13_1","volume-title":"Fast computation of the multi-points expected improvement with applications in batch selection. 01","author":"Chevalier Cl\u00e9ment","year":"2013","unstructured":"Cl\u00e9ment Chevalier . Fast computation of the multi-points expected improvement with applications in batch selection. 01 2013 . Cl\u00e9ment Chevalier. Fast computation of the multi-points expected improvement with applications in batch selection. 01 2013."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/2627435.2750368"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-40988-2_15"},{"key":"e_1_3_2_1_16_1","first-page":"3306","volume-title":"Proceedings of the 35th International Conference on Machine Learning, volume 80 of Proceedings of Machine Learning Research","author":"Lyu Wenlong","year":"2018","unstructured":"Wenlong Lyu , Fan Yang , Changhao Yan , Dian Zhou , and Xuan Zeng . Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design . In Proceedings of the 35th International Conference on Machine Learning, volume 80 of Proceedings of Machine Learning Research , pages 3306 -- 3314 , Stockholmsm\u00e4ssan, Stockholm Sweden , 10-15 Jul 2018 . Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, and Xuan Zeng. Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design. In Proceedings of the 35th International Conference on Machine Learning, volume 80 of Proceedings of Machine Learning Research, pages 3306--3314, Stockholmsm\u00e4ssan, Stockholm Sweden, 10-15 Jul 2018."},{"key":"e_1_3_2_1_17_1","first-page":"648","volume-title":"Artificial Intelligence and Statistics","author":"Gonz\u00e1lez Javier","year":"2016","unstructured":"Javier Gonz\u00e1lez , Zhenwen Dai , Philipp Hennig , and Neil Lawrence . Batch bayesian optimization via local penalization . In Artificial Intelligence and Statistics , pages 648 -- 657 , 2016 . Javier Gonz\u00e1lez, Zhenwen Dai, Philipp Hennig, and Neil Lawrence. Batch bayesian optimization via local penalization. In Artificial Intelligence and Statistics, pages 648--657, 2016."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008306431147"},{"key":"e_1_3_2_1_19_1","first-page":"1463","volume-title":"Automation Test in Europe Conference Exhibition (DATE)","author":"Zhang S.","year":"2019","unstructured":"S. Zhang , W. Lyu , F. Yang , C. Yan , D. Zhou , and X. Zeng . Bayesian optimization approach for analog circuit synthesis using neural network. In 2019 Design , Automation Test in Europe Conference Exhibition (DATE) , pages 1463 -- 1468 , 2019 . S. Zhang, W. Lyu, F. Yang, C. Yan, D. Zhou, and X. Zeng. Bayesian optimization approach for analog circuit synthesis using neural network. In 2019 Design, Automation Test in Europe Conference Exhibition (DATE), pages 1463--1468, 2019."},{"key":"e_1_3_2_1_20_1","first-page":"451","volume-title":"Proceedings of the 13th International Conference on Neural Information Processing Systems, NIPS'00","author":"Dugas Charles","year":"2000","unstructured":"Charles Dugas , Yoshua Bengio , Fran\u00e7ois B\u00e9lisle , Claude Nadeau , and Ren\u00e9 Garcia . Incorporating second-order functional knowledge for better option pricing . In Proceedings of the 13th International Conference on Neural Information Processing Systems, NIPS'00 , page 451 - 457 . MIT Press , 2000 . Charles Dugas, Yoshua Bengio, Fran\u00e7ois B\u00e9lisle, Claude Nadeau, and Ren\u00e9 Garcia. Incorporating second-order functional knowledge for better option pricing. In Proceedings of the 13th International Conference on Neural Information Processing Systems, NIPS'00, page 451-457. MIT Press, 2000."},{"key":"e_1_3_2_1_21_1","first-page":"3100","volume-title":"Encyclopedia of Optimization","author":"Pardalos P","year":"2008","unstructured":"P Pardalos and C Floudas . Encyclopedia of Optimization , pages 3100 -- 3105 . 01 2008 . P Pardalos and C Floudas. Encyclopedia of Optimization, pages 3100--3105. 01 2008."},{"key":"e_1_3_2_1_22_1","first-page":"1","volume-title":"2014 51st ACM\/EDAC\/IEEE Design Automation Conference (DAC)","author":"Wang Y.","year":"2014","unstructured":"Y. Wang , M. Orshansky , and C. Caramanis . Enabling efficient analog synthesis by coupling sparse regression and polynomial optimization . In 2014 51st ACM\/EDAC\/IEEE Design Automation Conference (DAC) , pages 1 -- 6 , 2014 . Y. Wang, M. Orshansky, and C. Caramanis. Enabling efficient analog synthesis by coupling sparse regression and polynomial optimization. In 2014 51st ACM\/EDAC\/IEEE Design Automation Conference (DAC), pages 1--6, 2014."}],"event":{"name":"ASPDAC '21: 26th Asia and South Pacific Design Automation Conference","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA"],"location":"Tokyo Japan","acronym":"ASPDAC '21"},"container-title":["Proceedings of the 26th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3394885.3431543","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3394885.3431543","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:32:02Z","timestamp":1750195922000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3394885.3431543"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1,18]]},"references-count":22,"alternative-id":["10.1145\/3394885.3431543","10.1145\/3394885"],"URL":"https:\/\/doi.org\/10.1145\/3394885.3431543","relation":{},"subject":[],"published":{"date-parts":[[2021,1,18]]},"assertion":[{"value":"2021-01-29","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}