{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,10]],"date-time":"2026-07-10T20:07:42Z","timestamp":1783714062138,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":34,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,1,18]],"date-time":"2021-01-18T00:00:00Z","timestamp":1610928000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100002347","name":"Bundesministerium f\u00fcr Bildung und Forschung","doi-asserted-by":"publisher","award":["01IW19001,16ME0127"],"award-info":[{"award-number":["01IW19001,16ME0127"]}],"id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,1,18]]},"DOI":"10.1145\/3394885.3431584","type":"proceedings-article","created":{"date-parts":[[2021,1,29]],"date-time":"2021-01-29T11:32:46Z","timestamp":1611919966000},"page":"55-60","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Mutation-based Compliance Testing for RISC-V"],"prefix":"10.1145","author":[{"given":"Vladimir","family":"Herdt","sequence":"first","affiliation":[{"name":"Institute of Computer Science, University of Bremen, Cyber-Physical Systems, DFKI GmbH, Bremen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"S\u00f6ren","family":"Tempel","sequence":"additional","affiliation":[{"name":"Institute of Computer Science, University of Bremen, Bremen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Daniel","family":"Gro\u00dfe","sequence":"additional","affiliation":[{"name":"Institute for Complex Systems, Johannes Kepler University Linz, Austria Cyber-Physical Systems, DFKI GmbH Bremen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[{"name":"Institute of Computer Science, University of Bremen, Cyber-Physical Systems, DFKI GmbH, Bremen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2021,1,29]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2017. RISC-V Torture Test Generator. https:\/\/github.com\/ucb-bar\/riscv-torture.  2017. RISC-V Torture Test Generator. https:\/\/github.com\/ucb-bar\/riscv-torture."},{"key":"e_1_3_2_1_2_1","unstructured":"2019. The Challenge Of RISC-V Compliance. https:\/\/semiengineering.com\/toward-risc-v-compliance\/.  2019. The Challenge Of RISC-V Compliance. https:\/\/semiengineering.com\/toward-risc-v-compliance\/."},{"key":"e_1_3_2_1_3_1","unstructured":"2019. Imperas delivers highest quality RISC-V RV32I compliance test suites to implementers and adopters of RISC-V. https:\/\/riscv.org\/2019\/11\/imperas-delivers-highest-quality-risc-v-rv32i-compliance-test-suites-to-implementers-and-adopters-of-risc-v\/.  2019. Imperas delivers highest quality RISC-V RV32I compliance test suites to implementers and adopters of RISC-V. https:\/\/riscv.org\/2019\/11\/imperas-delivers-highest-quality-risc-v-rv32i-compliance-test-suites-to-implementers-and-adopters-of-risc-v\/."},{"key":"e_1_3_2_1_4_1","unstructured":"2020. angr. https:\/\/angr.io\/.  2020. angr. https:\/\/angr.io\/."},{"key":"e_1_3_2_1_5_1","unstructured":"2020. GRIFT-Galois RISC-V ISA Formal Tools. https:\/\/github.com\/GaloisInc\/grift.  2020. GRIFT-Galois RISC-V ISA Formal Tools. https:\/\/github.com\/GaloisInc\/grift."},{"key":"e_1_3_2_1_6_1","unstructured":"2020. OneSpin 360 DV RISC-V Verification App. https:\/\/www.onespin.com\/solutions\/risc-v.  2020. OneSpin 360 DV RISC-V Verification App. https:\/\/www.onespin.com\/solutions\/risc-v."},{"key":"e_1_3_2_1_7_1","unstructured":"2020. RISC-V Compliance Task Group. https:\/\/github.com\/riscv\/riscv-compliance.  2020. RISC-V Compliance Task Group. https:\/\/github.com\/riscv\/riscv-compliance."},{"key":"e_1_3_2_1_8_1","unstructured":"2020. RISC-V Formal Verification Framework. https:\/\/github.com\/SymbioticEDA\/riscv-formal.  2020. RISC-V Formal Verification Framework. https:\/\/github.com\/SymbioticEDA\/riscv-formal."},{"key":"e_1_3_2_1_9_1","unstructured":"2020. RISC-V Virtual Prototype. https:\/\/github.com\/agra-uni-bremen\/riscv-vp.  2020. RISC-V Virtual Prototype. https:\/\/github.com\/agra-uni-bremen\/riscv-vp."},{"key":"e_1_3_2_1_10_1","unstructured":"2020. RISCV-DV. https:\/\/github.com\/google\/riscv-dv.  2020. RISCV-DV. https:\/\/github.com\/google\/riscv-dv."},{"key":"e_1_3_2_1_11_1","unstructured":"2020. RISCV Sail Model. https:\/\/github.com\/rems-project\/sail-riscv.  2020. RISCV Sail Model. https:\/\/github.com\/rems-project\/sail-riscv."},{"key":"e_1_3_2_1_12_1","unstructured":"2020. Spike RISC-VISA Simulator. https:\/\/github.com\/riscv\/riscv-isa-sim.  2020. Spike RISC-VISA Simulator. https:\/\/github.com\/riscv\/riscv-isa-sim."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"crossref","unstructured":"A. Adir E. Almog L. Fournier E. Marcus M. Rimon M. Vinov and A. Ziv. 2004. Genesys-Pro: innovations in test program generation for functional processor verification. D&T (2004) 84--93.  A. Adir E. Almog L. Fournier E. Marcus M. Rimon M. Vinov and A. Ziv. 2004. Genesys-Pro: innovations in test program generation for functional processor verification. D&T (2004) 84--93.","DOI":"10.1109\/MDT.2004.1277900"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"crossref","unstructured":"Brian Campbell and Ian Stark. 2014. Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation. In Formal Methods for Industrial Critical Systems Fr\u00e9d\u00e9ric Lang and Francesco Flammini (Eds.). 185--199.  Brian Campbell and Ian Stark. 2014. Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation. In Formal Methods for Industrial Critical Systems Fr\u00e9d\u00e9ric Lang and Francesco Flammini (Eds.). 185--199.","DOI":"10.1007\/978-3-319-10702-8_13"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"Mikhail Chupilko Alexander Kamkin Artem Kotsynyak and Andrei Tatarnikov. 2017. MicroTESK: Specification-Based Tool for Constructing Test Program Generators. In HVC.  Mikhail Chupilko Alexander Kamkin Artem Kotsynyak and Andrei Tatarnikov. 2017. MicroTESK: Specification-Based Tool for Constructing Test Program Generators. In HVC.","DOI":"10.1007\/978-3-319-70389-3_15"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"crossref","unstructured":"S. Fine and A. Ziv. 2003. Coverage directed test generation for functional verification using Bayesian networks. In DAC. 286--291.  S. Fine and A. Ziv. 2003. Coverage directed test generation for functional verification using Bayesian networks. In DAC. 286--291.","DOI":"10.1145\/775832.775907"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"crossref","unstructured":"Mark Hampton and Stephane Petithomme. 2007. Leveraging a Commercial Mutation Analysis Tool For Research. In MUTATION. 203--209.  Mark Hampton and Stephane Petithomme. 2007. Leveraging a Commercial Mutation Analysis Tool For Research. In MUTATION. 203--209.","DOI":"10.1109\/TAIC.PART.2007.39"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"Vladimir Herdt Daniel Gro\u00dfe and Rolf Drechsler. 2020. Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side. In DAC.  Vladimir Herdt Daniel Gro\u00dfe and Rolf Drechsler. 2020. Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side. In DAC.","DOI":"10.1109\/DAC18072.2020.9218629"},{"key":"e_1_3_2_1_19_1","volume-title":"Enhanced Virtual Prototyping: Featuring RISC-V Case Studies","author":"Herdt Vladimir","unstructured":"Vladimir Herdt , Daniel Gro\u00dfe , and Rolf Drechsler . 2020. Enhanced Virtual Prototyping: Featuring RISC-V Case Studies . Springer . Vladimir Herdt, Daniel Gro\u00dfe, and Rolf Drechsler. 2020. Enhanced Virtual Prototyping: Featuring RISC-V Case Studies. Springer."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"crossref","unstructured":"Vladimir Herdt Daniel Gro\u00dfe and Rolf Drechsler. 2020. Towards Specification and Testing of RISC-V ISA Compliance. In DATE. 995--998.  Vladimir Herdt Daniel Gro\u00dfe and Rolf Drechsler. 2020. Towards Specification and Testing of RISC-V ISA Compliance. In DATE. 995--998.","DOI":"10.23919\/DATE48585.2020.9116193"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"crossref","unstructured":"Vladimir Herdt Daniel Gro\u00dfe Hoang M. Le and Rolf Drechsler. 2018. Extensible and Configurable RISC-V based Virtual Prototype. In FDL. 5--16.  Vladimir Herdt Daniel Gro\u00dfe Hoang M. Le and Rolf Drechsler. 2018. Extensible and Configurable RISC-V based Virtual Prototype. In FDL. 5--16.","DOI":"10.1109\/FDL.2018.8524047"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"crossref","unstructured":"Vladimir Herdt Daniel Gro\u00dfe Hoang M. Le and Rolf Drechsler. 2019. Verifying Instruction Set Simulators using Coverage-guided Fuzzing. In DATE. 360--365.  Vladimir Herdt Daniel Gro\u00dfe Hoang M. Le and Rolf Drechsler. 2019. Verifying Instruction Set Simulators using Coverage-guided Fuzzing. In DATE. 360--365.","DOI":"10.23919\/DATE.2019.8714912"},{"key":"e_1_3_2_1_23_1","volume-title":"RISC-V based Virtual Prototype: An Extensible and Configurable Platform for the System-level. JSA","author":"Herdt Vladimir","year":"2020","unstructured":"Vladimir Herdt , Daniel Gro\u00dfe , Pascal Pieper , and Rolf Drechsler . 2020. RISC-V based Virtual Prototype: An Extensible and Configurable Platform for the System-level. JSA ( 2020 ). Vladimir Herdt, Daniel Gro\u00dfe, Pascal Pieper, and Rolf Drechsler. 2020. RISC-V based Virtual Prototype: An Extensible and Configurable Platform for the System-level. JSA (2020)."},{"key":"e_1_3_2_1_24_1","first-page":"1359","article-title":"Verifying SystemC using Intermediate Verification Language and Stateful Symbolic Simulation","volume":"38","author":"Herdt Vladimir","year":"2019","unstructured":"Vladimir Herdt , Hoang M. Le , Daniel Gro\u00dfe , and Rolf Drechsler . 2019 . Verifying SystemC using Intermediate Verification Language and Stateful Symbolic Simulation . TCAD 38 , 7 (2019), 1359 -- 1372 . Vladimir Herdt, Hoang M. Le, Daniel Gro\u00dfe, and Rolf Drechsler. 2019. Verifying SystemC using Intermediate Verification Language and Stateful Symbolic Simulation. TCAD 38, 7 (2019), 1359--1372.","journal-title":"TCAD"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"crossref","unstructured":"Charalambos Ioannides Geoff Barrett and Kerstin Eder. 2011. Feedback-Based Coverage Directed Test Generation: An Industrial Evaluation. In Hardware and Software: Verification and Testing Sharon Barner Ian Harris Daniel Kroening and Orna Raz (Eds.).  Charalambos Ioannides Geoff Barrett and Kerstin Eder. 2011. Feedback-Based Coverage Directed Test Generation: An Industrial Evaluation. In Hardware and Software: Verification and Testing Sharon Barner Ian Harris Daniel Kroening and Orna Raz (Eds.).","DOI":"10.1007\/978-3-642-19583-9_13"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.2010.62"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","unstructured":"Y. Katz M. Rimon and A. Ziv.2012. Generating instruction streams using abstract CSP. In DATE. 15--20.  Y. Katz M. Rimon and A. Ziv.2012. Generating instruction streams using abstract CSP. In DATE. 15--20.","DOI":"10.1109\/DATE.2012.6176425"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"crossref","unstructured":"Lingyi Liu and Shobha Vasudevan. 2011. Efficient validation input generation in RTL by hybridized source code analysis. In DATE. 1596--1601.  Lingyi Liu and Shobha Vasudevan. 2011. Efficient validation input generation in RTL by hybridized source code analysis. In DATE. 1596--1601.","DOI":"10.1109\/DATE.2011.5763253"},{"key":"e_1_3_2_1_29_1","volume-title":"Giampaolo Fresi Roglia, and Danilo Bruschi","author":"Martignoni Lorenzo","year":"2009","unstructured":"Lorenzo Martignoni , Roberto Paleari , Giampaolo Fresi Roglia, and Danilo Bruschi . 2009 . Testing CPU Emulators. In ISSTA. 261--272. Lorenzo Martignoni, Roberto Paleari, Giampaolo Fresi Roglia, and Danilo Bruschi. 2009. Testing CPU Emulators. In ISSTA. 261--272."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"crossref","unstructured":"Youssef Serrestou Vincent Beroulle and Chantal Robach. 2007. Functional Verification of RTL Designs Driven by Mutation Testing Metrics. In DSD. 222--227.  Youssef Serrestou Vincent Beroulle and Chantal Robach. 2007. Functional Verification of RTL Designs Driven by Mutation Testing Metrics. In DSD. 222--227.","DOI":"10.1109\/DSD.2007.4341472"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"crossref","unstructured":"Yan Shoshitaishvili Ruoyu Wang Christopher Salls Nick Stephens Mario Polino Audrey Dutcher John Grosen Siji Feng Christophe Hauser Christopher Kruegel and Giovanni Vigna. 2016. SoK: (State of) The Art of War: Offensive Techniques in Binary Analysis. (2016).  Yan Shoshitaishvili Ruoyu Wang Christopher Salls Nick Stephens Mario Polino Audrey Dutcher John Grosen Siji Feng Christophe Hauser Christopher Kruegel and Giovanni Vigna. 2016. SoK: (State of) The Art of War: Offensive Techniques in Binary Analysis. (2016).","DOI":"10.1109\/SP.2016.17"},{"key":"e_1_3_2_1_32_1","volume-title":"The RISC-V Instruction Set Manual","author":"Waterman Andrew","unstructured":"Andrew Waterman and Krste Asanovi\u0107 . 2019. The RISC-V Instruction Set Manual ; Volume I: Unprivileged ISA. SiFive Inc. and CS Division, EECS Department, University of California , Berkeley. Andrew Waterman and Krste Asanovi\u0107. 2019. The RISC-V Instruction Set Manual; Volume I: Unprivileged ISA. SiFive Inc. and CS Division, EECS Department, University of California, Berkeley."},{"key":"e_1_3_2_1_33_1","volume-title":"The RISC-V Instruction Set Manual","author":"Waterman Andrew","unstructured":"Andrew Waterman and Krste Asanovi\u0107 . 2019. The RISC-V Instruction Set Manual ; Volume II : Privileged Architecture. SiFive Inc. and CS Division, EECS Department, University of California , Berkeley. Andrew Waterman and Krste Asanovi\u0107. 2019. The RISC-V Instruction Set Manual; Volume II: Privileged Architecture. SiFive Inc. and CS Division, EECS Department, University of California, Berkeley."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"crossref","unstructured":"Tao Xie Wolfgang Mueller and Florian Letombe. 2012. Mutation-analysis driven functional verification of a soft microprocessor. In SoC. 283--288.  Tao Xie Wolfgang Mueller and Florian Letombe. 2012. Mutation-analysis driven functional verification of a soft microprocessor. In SoC. 283--288.","DOI":"10.1109\/SOCC.2012.6398362"}],"event":{"name":"ASPDAC '21: 26th Asia and South Pacific Design Automation Conference","location":"Tokyo Japan","acronym":"ASPDAC '21","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA"]},"container-title":["Proceedings of the 26th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3394885.3431584","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3394885.3431584","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:32:02Z","timestamp":1750195922000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3394885.3431584"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1,18]]},"references-count":34,"alternative-id":["10.1145\/3394885.3431584","10.1145\/3394885"],"URL":"https:\/\/doi.org\/10.1145\/3394885.3431584","relation":{},"subject":[],"published":{"date-parts":[[2021,1,18]]},"assertion":[{"value":"2021-01-29","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}