{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T15:53:44Z","timestamp":1774367624314,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":57,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,1,18]],"date-time":"2021-01-18T00:00:00Z","timestamp":1610928000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,1,18]]},"DOI":"10.1145\/3394885.3431625","type":"proceedings-article","created":{"date-parts":[[2021,1,29]],"date-time":"2021-01-29T11:32:48Z","timestamp":1611919968000},"page":"833-840","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Physical Synthesis for Advanced Neural Network Processors"],"prefix":"10.1145","author":[{"given":"Zhuolun","family":"He","sequence":"first","affiliation":[{"name":"Chinese University of Hong Kong"}]},{"given":"Peiyu","family":"Liao","sequence":"additional","affiliation":[{"name":"Chinese University of Hong Kong"}]},{"given":"Siting","family":"Liu","sequence":"additional","affiliation":[{"name":"Chinese University of Hong Kong"}]},{"given":"Yuzhe","family":"Ma","sequence":"additional","affiliation":[{"name":"Chinese University of Hong Kong"}]},{"given":"Yibo","family":"Lin","sequence":"additional","affiliation":[{"name":"Peking University"}]},{"given":"Bei","family":"Yu","sequence":"additional","affiliation":[{"name":"Chinese University of Hong Kong"}]}],"member":"320","published-online":{"date-parts":[[2021,1,29]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783725"},{"key":"e_1_3_2_1_3_1","volume-title":"FPGA","author":"Ma Y.","year":"2017"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240801"},{"key":"e_1_3_2_1_5_1","volume-title":"DAC","author":"Wei X.","year":"2017"},{"key":"e_1_3_2_1_6_1","volume-title":"ICCAD","author":"Sun Q.","year":"2019"},{"key":"e_1_3_2_1_7_1","volume-title":"Devices & Systems","author":"Wang Y.","year":"2017"},{"key":"e_1_3_2_1_8_1","volume-title":"DAC","author":"Cai H.","year":"1990"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"Y.-W. Tsay and Y.-L. Lin \"A row-based cell placement method that utilizes circuit structural properties \" IEEE TCAD 1995.  Y.-W. Tsay and Y.-L. Lin \"A row-based cell placement method that utilizes circuit structural properties \" IEEE TCAD 1995.","DOI":"10.1109\/43.365130"},{"key":"e_1_3_2_1_10_1","volume-title":"ICCAD","author":"Ye T. T.","year":"2000"},{"key":"e_1_3_2_1_11_1","volume-title":"DATE","author":"Serdar T.","year":"2001"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309928"},{"key":"e_1_3_2_1_13_1","volume-title":"Challenges to data-path physical design inside SOC,\" CHINESE JOURNAL OF SEMICONDUCTORS-CHINESE EDITION-","author":"Tong J.","year":"2002"},{"key":"e_1_3_2_1_14_1","volume-title":"ICCCAS","author":"Jing T.","year":"2002"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717775"},{"key":"e_1_3_2_1_16_1","volume-title":"ISCAS","volume":"3","author":"Ye T. T.","year":"2002"},{"key":"e_1_3_2_1_17_1","volume-title":"DAC","author":"Chou S.","year":"2012"},{"key":"e_1_3_2_1_18_1","volume-title":"ISCAS","author":"Zhang J.","year":"2019"},{"key":"e_1_3_2_1_19_1","volume-title":"ASPDAC","volume":"1","author":"Ono S.","year":"2005"},{"key":"e_1_3_2_1_20_1","volume-title":"ISPD","author":"Ward S. I.","year":"2011"},{"key":"e_1_3_2_1_21_1","volume-title":"IWLS","author":"Nijssen R. X.","year":"1996"},{"key":"e_1_3_2_1_22_1","volume-title":"ICCAD","volume":"97","author":"Arikati S. R.","year":"1997"},{"key":"e_1_3_2_1_23_1","volume-title":"Extraction of functional regularity in datapath circuits,\" IEEE TCAD","author":"Chowdhary A.","year":"1999"},{"key":"e_1_3_2_1_24_1","volume-title":"ISPD","author":"Xiang H.","year":"2013"},{"key":"e_1_3_2_1_25_1","volume-title":"DAC","author":"Huang C.-C.","year":"2017"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2000.896511"},{"key":"e_1_3_2_1_27_1","volume-title":"ICCD","author":"Kutzschebauch T.","year":"2000"},{"key":"e_1_3_2_1_28_1","volume-title":"ISVLSI","author":"Rosiello A. P.","year":"2007"},{"key":"e_1_3_2_1_29_1","volume-title":"DAC","author":"Ienne P.","year":"1998"},{"key":"e_1_3_2_1_30_1","volume-title":"DAC","author":"Ward S.","year":"2012"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160935"},{"key":"e_1_3_2_1_32_1","volume-title":"Structure-aware placement techniques for designs with datapaths,\" IEEE TCAD","author":"Ward S. I.","year":"2013"},{"key":"e_1_3_2_1_33_1","unstructured":"\"ISPD 2020 contest: Wafer-scale deep learning accelerator placement \" https:\/\/www.cerebras.net\/ispd-2020-contest\/.  \"ISPD 2020 contest: Wafer-scale deep learning accelerator placement \" https:\/\/www.cerebras.net\/ispd-2020-contest\/."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415688"},{"key":"e_1_3_2_1_35_1","volume-title":"Twin binary sequences: a nonredundant representation for general nonslicing floorplan,\" IEEE TCAD","author":"Young E. F.","year":"2003"},{"key":"e_1_3_2_1_36_1","volume-title":"Emerging neuromorphic devices,\" Nanotechnology","author":"Ielmini D.","year":"2019"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2019.000-8"},{"key":"e_1_3_2_1_38_1","volume-title":"PRIME: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory,\" ACM SIGARCH Computer Architecture News","author":"Chi P.","year":"2016"},{"key":"e_1_3_2_1_39_1","volume-title":"DATE","author":"Sun X.","year":"2018"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3205289.3205297"},{"key":"e_1_3_2_1_41_1","author":"Pan Y.","year":"2018","journal-title":"\"A multilevel cell STT-MRAM-based computing in-memory accelerator for binary convolutional neural network,\" IEEE Transactions on Magnetics"},{"key":"e_1_3_2_1_42_1","volume-title":"DATE","author":"Kim B.","year":"2020"},{"key":"e_1_3_2_1_43_1","volume-title":"Fully hardware-implemented memristor convolutional neural network,\" Nature","author":"Yao P.","year":"2020"},{"key":"e_1_3_2_1_44_1","volume-title":"Wang et al., \"Efficient and self-adaptive in-situ learning in multilayer memristor neural networks,\" Nature communications","author":"Li C.","year":"2018"},{"key":"e_1_3_2_1_45_1","volume-title":"Reproducible ultrathin ferroelectric domain switching for high-performance neuromorphic computing,\" Advanced Materials","author":"Li J.","year":"2020"},{"key":"e_1_3_2_1_46_1","volume-title":"Englund et al., \"Deep learning with coherent nanophotonic circuits,\" Nature Photonics","author":"Shen Y.","year":"2017"},{"key":"e_1_3_2_1_47_1","volume-title":"All-optical neural network with nonlinear activation functions,\" Optica","author":"Zuo Y.","year":"2019"},{"key":"e_1_3_2_1_48_1","volume-title":"ASPDAC","author":"Gu J.","year":"2020"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037702"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"e_1_3_2_1_51_1","volume-title":"ISSCC","author":"Lee D. U.","year":"2014"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310261"},{"key":"e_1_3_2_1_53_1","volume-title":"ISLPED","author":"Chang K.","year":"2017"},{"key":"e_1_3_2_1_54_1","volume-title":"Power, performance, and area benefit of monolithic 3D ICs for on-chip deep neural networks targeting speech recognition,\" ACM JETC","author":"Chang K.","year":"2018"},{"key":"e_1_3_2_1_55_1","volume-title":"Chiarulli et al., \"Enabling new computation paradigms with HyperFET-an emerging device,\" IEEE TMSCS","author":"Tsai W.-Y.","year":"2016"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2013.6629301"},{"key":"e_1_3_2_1_57_1","volume-title":"Two-dimensional materials for next-generation computing technologies,\" Nature Nanotechnology","author":"Liu C.","year":"2020"}],"event":{"name":"ASPDAC '21: 26th Asia and South Pacific Design Automation Conference","location":"Tokyo Japan","acronym":"ASPDAC '21","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA"]},"container-title":["Proceedings of the 26th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3394885.3431625","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3394885.3431625","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:47:59Z","timestamp":1750193279000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3394885.3431625"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1,18]]},"references-count":57,"alternative-id":["10.1145\/3394885.3431625","10.1145\/3394885"],"URL":"https:\/\/doi.org\/10.1145\/3394885.3431625","relation":{},"subject":[],"published":{"date-parts":[[2021,1,18]]},"assertion":[{"value":"2021-01-29","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}